Search

Huan Hoang

Examiner (ID: 15690, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827, 2511, 2818, 2154
Total Applications
3289
Issued Applications
3066
Pending Applications
115
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17623291 [patent_doc_number] => 11342356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator [patent_app_type] => utility [patent_app_number] => 17/141495 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141495
Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator Jan 4, 2021 Issued
Array ( [id] => 17924715 [patent_doc_number] => 11467965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Processing-in-memory (PIM) device [patent_app_type] => utility [patent_app_number] => 17/138501 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 29741 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138501
Processing-in-memory (PIM) device Dec 29, 2020 Issued
Array ( [id] => 18235743 [patent_doc_number] => 11600307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Memory circuit architecture [patent_app_type] => utility [patent_app_number] => 17/136616 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8900 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136616 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136616
Memory circuit architecture Dec 28, 2020 Issued
Array ( [id] => 17558891 [patent_doc_number] => 11315610 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-26 [patent_title] => Sense amplifier, memory and method for controlling sense amplifier [patent_app_type] => utility [patent_app_number] => 17/441676 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7310 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17441676 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/441676
Sense amplifier, memory and method for controlling sense amplifier Dec 24, 2020 Issued
Array ( [id] => 16765289 [patent_doc_number] => 20210110871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => ELECTRONIC DEVICE AND METHOD OF OPERATING MEMORY CELL IN THE ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/131456 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131456 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131456
Electronic device and method of operating memory cell in the electronic device Dec 21, 2020 Issued
Array ( [id] => 17203230 [patent_doc_number] => 20210343325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => MEMORY DEVICE FOR REDUCING RESOURCES USED FOR TRAINING [patent_app_type] => utility [patent_app_number] => 17/130493 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130493
Memory device for reducing resources used for training Dec 21, 2020 Issued
Array ( [id] => 16934403 [patent_doc_number] => 20210200292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => POWER DELIVERY TIMING FOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/126651 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126651
Power delivery timing for memory Dec 17, 2020 Issued
Array ( [id] => 17438739 [patent_doc_number] => 11264079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-01 [patent_title] => Apparatuses and methods for row hammer based cache lockdown [patent_app_type] => utility [patent_app_number] => 17/127654 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127654
Apparatuses and methods for row hammer based cache lockdown Dec 17, 2020 Issued
Array ( [id] => 16752518 [patent_doc_number] => 20210104530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => SRAM Structure and Connection [patent_app_type] => utility [patent_app_number] => 17/121254 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121254
SRAM structure and connection Dec 13, 2020 Issued
Array ( [id] => 17469994 [patent_doc_number] => 11276476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-15 [patent_title] => Common-mode comparison based fuse-readout circuit [patent_app_type] => utility [patent_app_number] => 17/117877 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117877 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117877
Common-mode comparison based fuse-readout circuit Dec 9, 2020 Issued
Array ( [id] => 17500426 [patent_doc_number] => 11289135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Precharge timing control [patent_app_type] => utility [patent_app_number] => 17/115327 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115327
Precharge timing control Dec 7, 2020 Issued
Array ( [id] => 17660449 [patent_doc_number] => 20220180914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => APPARATUSES AND METHODS FOR PROVIDING POWER RESPONSIVE TO INTERNAL POWER USAGE [patent_app_type] => utility [patent_app_number] => 17/114338 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114338
Apparatuses and methods for providing power responsive to internal power usage Dec 6, 2020 Issued
Array ( [id] => 18000717 [patent_doc_number] => 11501828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Apparatuses, memories, and methods for address decoding and selecting an access line [patent_app_type] => utility [patent_app_number] => 17/107639 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5476 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107639
Apparatuses, memories, and methods for address decoding and selecting an access line Nov 29, 2020 Issued
Array ( [id] => 16715383 [patent_doc_number] => 20210082530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/107317 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107317
Semiconductor memory device and operating method thereof Nov 29, 2020 Issued
Array ( [id] => 17516638 [patent_doc_number] => 11295797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Techniques to mitigate asymmetric long delay stress [patent_app_type] => utility [patent_app_number] => 17/103552 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13924 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103552
Techniques to mitigate asymmetric long delay stress Nov 23, 2020 Issued
Array ( [id] => 17380883 [patent_doc_number] => 11238904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Using embedded switches for reducing capacitive loading on a memory system [patent_app_type] => utility [patent_app_number] => 17/103767 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103767 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103767
Using embedded switches for reducing capacitive loading on a memory system Nov 23, 2020 Issued
Array ( [id] => 16850342 [patent_doc_number] => 20210151087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => APPARATUSES AND METHODS FOR CLOCK LEVELING IN SEMICONDUCTOR MEMORIES [patent_app_type] => utility [patent_app_number] => 17/097717 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097717
Apparatuses and methods for clock leveling in semiconductor memories Nov 12, 2020 Issued
Array ( [id] => 17908398 [patent_doc_number] => 11462258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/097849 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5750 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097849
Memory device and operation method thereof Nov 12, 2020 Issued
Array ( [id] => 18000710 [patent_doc_number] => 11501821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same [patent_app_type] => utility [patent_app_number] => 17/090080 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 17886 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/090080
Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same Nov 4, 2020 Issued
Array ( [id] => 17224481 [patent_doc_number] => 11176991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Compute-in-memory (CIM) employing low-power CIM circuits employing static random access memory (SRAM) bit cells, particularly for multiply-and-accumluate (MAC) operations [patent_app_type] => utility [patent_app_number] => 17/084779 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15899 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084779
Compute-in-memory (CIM) employing low-power CIM circuits employing static random access memory (SRAM) bit cells, particularly for multiply-and-accumluate (MAC) operations Oct 29, 2020 Issued
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