Search

Huan Hoang

Examiner (ID: 18810, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2154, 2827, 2511
Total Applications
3293
Issued Applications
3069
Pending Applications
116
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19865960 [patent_doc_number] => 20250104746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/829789 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/829789
Memory and operating method thereof Sep 9, 2024 Issued
Array ( [id] => 19661790 [patent_doc_number] => 20240428855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => MEMORY DEVICE, THE OPERATION METHOD THEREOF AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/826933 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826933
MEMORY DEVICE, THE OPERATION METHOD THEREOF AND MEMORY SYSTEM Sep 5, 2024 Pending
Array ( [id] => 19850380 [patent_doc_number] => 20250095731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => METHOD OF OPERATING PHASE CHANGE MEMORIES, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 18/824446 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 451 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/824446
METHOD OF OPERATING PHASE CHANGE MEMORIES, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT Sep 3, 2024 Pending
Array ( [id] => 20396704 [patent_doc_number] => 20250372179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY SYSTEMS, OPERATION METHODS THEREOF, AND COMPUTER READABLE STORAGE MEDIA [patent_app_type] => utility [patent_app_number] => 18/822074 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18822074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/822074
MEMORY SYSTEMS, OPERATION METHODS THEREOF, AND COMPUTER READABLE STORAGE MEDIA Aug 29, 2024 Pending
Array ( [id] => 19803731 [patent_doc_number] => 20250069656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => NON-VOLATILE MEMORY DEVICE, CORRESPONDING METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/813662 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813662
NON-VOLATILE MEMORY DEVICE, CORRESPONDING METHOD AND SYSTEM Aug 22, 2024 Pending
Array ( [id] => 20516471 [patent_doc_number] => 20260040574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => MRAM Circuit and Layout [patent_app_type] => utility [patent_app_number] => 18/809277 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18809277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/809277
MRAM circuit and layout Aug 18, 2024 Issued
Array ( [id] => 19773101 [patent_doc_number] => 20250054527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SKIPPING PAGES FOR WEAK WORDLINES OF A MEMORY DEVICE DURING PRE-PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/806285 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18806285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/806285
SKIPPING PAGES FOR WEAK WORDLINES OF A MEMORY DEVICE DURING PRE-PROGRAMMING Aug 14, 2024 Pending
Array ( [id] => 19604431 [patent_doc_number] => 20240395311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => LOW POWER CLOCK INJECTION DURING IDLE MODE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/793311 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/793311
LOW POWER CLOCK INJECTION DURING IDLE MODE OPERATIONS Aug 1, 2024 Pending
Array ( [id] => 19604453 [patent_doc_number] => 20240395333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => FLOATING DATA LINE CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/790595 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790595 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790595
FLOATING DATA LINE CIRCUIT AND METHOD Jul 30, 2024 Pending
Array ( [id] => 20409779 [patent_doc_number] => 20250378888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => MANAGING WARMUP OPERATIONS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/791351 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791351
MANAGING WARMUP OPERATIONS IN A MEMORY DEVICE Jul 30, 2024 Pending
Array ( [id] => 19589366 [patent_doc_number] => 20240386923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => CONTENT ADDRESSABLE MEMORY FOR LARGE SEARCH WORDS [patent_app_type] => utility [patent_app_number] => 18/789540 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789540
CONTENT ADDRESSABLE MEMORY FOR LARGE SEARCH WORDS Jul 29, 2024 Pending
Array ( [id] => 19589422 [patent_doc_number] => 20240386979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => Bit Selection for Power Reduction in Stacking Structure During Memory Programming [patent_app_type] => utility [patent_app_number] => 18/786718 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786718
Bit Selection for Power Reduction in Stacking Structure During Memory Programming Jul 28, 2024 Pending
Array ( [id] => 19803704 [patent_doc_number] => 20250069629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => PROCESSING IN MEMORY REGISTERS [patent_app_type] => utility [patent_app_number] => 18/786480 [patent_app_country] => US [patent_app_date] => 2024-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786480 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786480
Processing in memory registers Jul 26, 2024 Issued
Array ( [id] => 19618886 [patent_doc_number] => 20240404566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL [patent_app_type] => utility [patent_app_number] => 18/783924 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783924
HEADER LAYOUT DESIGN INCLUDING BACKSIDE POWER RAIL Jul 24, 2024 Pending
Array ( [id] => 20352525 [patent_doc_number] => 20250349377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => ARRAY OF MULTI-VALUE NON-VOLATILE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/782022 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782022
ARRAY OF MULTI-VALUE NON-VOLATILE MEMORY CELLS Jul 22, 2024 Pending
Array ( [id] => 19711128 [patent_doc_number] => 20250021270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => INTERFACE CIRCUIT FOR CONVERTING A SERIAL DATA STREAM TO A PARALLEL DATA SCHEME WITH DATA STROBE PREAMBLE INFORMATION IN THE SERIAL DATA STREAM [patent_app_type] => utility [patent_app_number] => 18/779269 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779269 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779269
INTERFACE CIRCUIT FOR CONVERTING A SERIAL DATA STREAM TO A PARALLEL DATA SCHEME WITH DATA STROBE PREAMBLE INFORMATION IN THE SERIAL DATA STREAM Jul 21, 2024 Pending
Array ( [id] => 19803754 [patent_doc_number] => 20250069679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => VOLTAGE SCALING BASED ON ERROR RATE FLUCTUATIONS [patent_app_type] => utility [patent_app_number] => 18/774638 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774638 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774638
Voltage scaling based on error rate fluctuations Jul 15, 2024 Issued
Array ( [id] => 19726919 [patent_doc_number] => 20250029670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => METHODS OF OPERATING MAGNETIC MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/774226 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774226
Methods of operating magnetic memory devices Jul 15, 2024 Issued
Array ( [id] => 19559637 [patent_doc_number] => 20240371429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Memory Device [patent_app_type] => utility [patent_app_number] => 18/773269 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773269 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773269
Memory Device Jul 14, 2024 Pending
Array ( [id] => 19820732 [patent_doc_number] => 20250078939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => ENHANCED COMBINATION SCAN MANAGEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/771819 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771819
Enhanced combination scan management for block families of a memory device Jul 11, 2024 Issued
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