Huan Hoang

Array ( [id] => 17908398 [patent_doc_number] => 11462258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/097849 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5750 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16850342 [patent_doc_number] => 20210151087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => APPARATUSES AND METHODS FOR CLOCK LEVELING IN SEMICONDUCTOR MEMORIES [patent_app_type] => utility [patent_app_number] => 17/097717 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18000710 [patent_doc_number] => 11501821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same [patent_app_type] => utility [patent_app_number] => 17/090080 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 17886 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17757959 [patent_doc_number] => 11398257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Header layout design including backside power rail [patent_app_type] => utility [patent_app_number] => 17/085067 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17224481 [patent_doc_number] => 11176991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => Compute-in-memory (CIM) employing low-power CIM circuits employing static random access memory (SRAM) bit cells, particularly for multiply-and-accumluate (MAC) operations [patent_app_type] => utility [patent_app_number] => 17/084779 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15899 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17332238 [patent_doc_number] => 11222706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods [patent_app_type] => utility [patent_app_number] => 17/075002 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18721247 [patent_doc_number] => 11798599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Efficient placement of memory [patent_app_type] => utility [patent_app_number] => 17/763813 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5190 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17763813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17438755 [patent_doc_number] => 11264095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Electronic device and method of operating memory cell in the electronic device [patent_app_type] => utility [patent_app_number] => 17/039480 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10122 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17507657 [patent_doc_number] => 20220100760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => ACCELERATION OF DATA QUERIES IN MEMORY [patent_app_type] => utility [patent_app_number] => 17/033332 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17332229 [patent_doc_number] => 11222697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Three-dimensional nonvolatile memory and method of performing read operation in the nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/023002 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16528518 [patent_doc_number] => 20200402599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => Memory Device with a Fuse Protection Circuit [patent_app_type] => utility [patent_app_number] => 17/013967 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115338 [patent_doc_number] => 20210295935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD OF SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/012118 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17470332 [patent_doc_number] => 11276815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Spin-orbit torque type magnetization reversal element, magnetic memory, and high frequency magnetic device [patent_app_type] => utility [patent_app_number] => 17/010329 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 12287 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17825552 [patent_doc_number] => 11430504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Row clear features for memory devices and associated methods and systems [patent_app_type] => utility [patent_app_number] => 17/005034 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9608 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115295 [patent_doc_number] => 20210295892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/002512 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17447855 [patent_doc_number] => 20220068360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => PSEUDO-TRIPLE-PORT SRAM BITCELL ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/002082 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16509052 [patent_doc_number] => 20200388308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => LEAKAGE PATHWAY PREVENTION IN A MEMORY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/999867 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999867 [rel_patent_id] =>[rel_patent_doc_number] =>)