Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18827491 [patent_doc_number] => 11842780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Semiconductor device and electronic apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/439454 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 20301 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17439454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/439454
Semiconductor device and electronic apparatus including the same Jan 30, 2020 Issued
Array ( [id] => 17523254 [patent_doc_number] => 20220109103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => MAGNETIC MEMORY DEVICE USING DOPED SEMICONDUCTOR LAYER [patent_app_type] => utility [patent_app_number] => 17/426508 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17426508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/426508
Magnetic memory device using doped semiconductor layer Jan 30, 2020 Issued
Array ( [id] => 16544689 [patent_doc_number] => 20200411104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THEREOF [patent_app_type] => utility [patent_app_number] => 16/731288 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731288
Nonvolatile memory device and memory system including thereof Dec 30, 2019 Issued
Array ( [id] => 16521422 [patent_doc_number] => 10872645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-22 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/731848 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6779 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731848
Semiconductor devices Dec 30, 2019 Issued
Array ( [id] => 16936097 [patent_doc_number] => 20210201986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => MEMORY CONTEXT RESTORE, REDUCTION OF BOOT TIME OF A SYSTEM ON A CHIP BY REDUCING DOUBLE DATA RATE MEMORY TRAINING [patent_app_type] => utility [patent_app_number] => 16/730086 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730086 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730086
Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training Dec 29, 2019 Issued
Array ( [id] => 16534942 [patent_doc_number] => 10877541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Power delivery timing for memory [patent_app_type] => utility [patent_app_number] => 16/729808 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729808
Power delivery timing for memory Dec 29, 2019 Issued
Array ( [id] => 16509055 [patent_doc_number] => 20200388311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => ENABLE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/730206 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730206
Enable signal generation circuit and semiconductor apparatus using the same Dec 29, 2019 Issued
Array ( [id] => 17032553 [patent_doc_number] => 11094370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Enhanced auto-precharge memory scheduling policy [patent_app_type] => utility [patent_app_number] => 16/728679 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 15542 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728679
Enhanced auto-precharge memory scheduling policy Dec 26, 2019 Issued
Array ( [id] => 17485655 [patent_doc_number] => 20220093159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => A DRAM MEMORY [patent_app_type] => utility [patent_app_number] => 17/281206 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17281206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/281206
DRAM memory Dec 23, 2019 Issued
Array ( [id] => 17463427 [patent_doc_number] => 20220076733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/415664 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17415664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/415664
Signal development caching in a memory device Dec 19, 2019 Issued
Array ( [id] => 15806931 [patent_doc_number] => 20200126608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => APPARATUSES AND METHODS FOR DYNAMIC VOLTAGE AND FREQUENCY SWITCHING FOR DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 16/723386 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723386
Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory Dec 19, 2019 Issued
Array ( [id] => 16309380 [patent_doc_number] => 10778196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Reducing power consumption in a processor circuit [patent_app_type] => utility [patent_app_number] => 16/720017 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2720 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720017 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720017
Reducing power consumption in a processor circuit Dec 18, 2019 Issued
Array ( [id] => 16455768 [patent_doc_number] => 20200365194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => DATA SENSING CIRCUIT OF SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/710958 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710958
Data sensing circuit of semiconductor apparatus Dec 10, 2019 Issued
Array ( [id] => 16495477 [patent_doc_number] => 10861524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Magnetoresistive random access memory (MRAM) with OTP cells [patent_app_type] => utility [patent_app_number] => 16/710830 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710830 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710830
Magnetoresistive random access memory (MRAM) with OTP cells Dec 10, 2019 Issued
Array ( [id] => 16746498 [patent_doc_number] => 10971499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Unified micro system with memory IC and logic IC [patent_app_type] => utility [patent_app_number] => 16/708442 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6480 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16708442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/708442
Unified micro system with memory IC and logic IC Dec 9, 2019 Issued
Array ( [id] => 15745805 [patent_doc_number] => 20200111792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => NAND String Utilizing Floating Body Memory Cell [patent_app_type] => utility [patent_app_number] => 16/706148 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706148
NAND string utilizing floating body memory cell Dec 5, 2019 Issued
Array ( [id] => 18890844 [patent_doc_number] => 11869621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Storage device having multiple storage dies and identification method [patent_app_type] => utility [patent_app_number] => 17/413600 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4813 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/413600
Storage device having multiple storage dies and identification method Nov 20, 2019 Issued
Array ( [id] => 16850756 [patent_doc_number] => 20210151501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => ELECTRIC FIELD CONTROLLABLE SPIN FILTER TUNNEL JUNCTION MAGNETORESISTIVE MEMORY DEVICES AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/686860 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686860
Electric field controllable spin filter tunnel junction magnetoresistive memory devices and methods of making the same Nov 17, 2019 Issued
Array ( [id] => 16417619 [patent_doc_number] => 10825519 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-03 [patent_title] => Electronic device and method of operating memory cell in the electronic device [patent_app_type] => utility [patent_app_number] => 16/687384 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/687384
Electronic device and method of operating memory cell in the electronic device Nov 17, 2019 Issued
Array ( [id] => 16609038 [patent_doc_number] => 10910051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Method and electronic circuit for verifying operation performed by cell of RRAM [patent_app_type] => utility [patent_app_number] => 16/686196 [patent_app_country] => US [patent_app_date] => 2019-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/686196
Method and electronic circuit for verifying operation performed by cell of RRAM Nov 16, 2019 Issued
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