
Huan Hoang
Examiner (ID: 18810, Phone: (571)272-1779 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2154, 2827, 2511 |
| Total Applications | 3293 |
| Issued Applications | 3069 |
| Pending Applications | 116 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17262364
[patent_doc_number] => 20210375349
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => MULTI-STAGE VOLTAGE CONTROL FOR PEAK AND AVERAGE CURRENT REDUCTION OF OPEN BLOCKS
[patent_app_type] => utility
[patent_app_number] => 16/888571
[patent_app_country] => US
[patent_app_date] => 2020-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12568
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888571
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/888571 | Multi-stage voltage control for peak and average current reduction of open blocks | May 28, 2020 | Issued |
Array
(
[id] => 16865607
[patent_doc_number] => 11024358
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-06-01
[patent_title] => Differential compute-in-memory bitcell
[patent_app_type] => utility
[patent_app_number] => 16/885148
[patent_app_country] => US
[patent_app_date] => 2020-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6974
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885148
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/885148 | Differential compute-in-memory bitcell | May 26, 2020 | Issued |
Array
(
[id] => 17332217
[patent_doc_number] => 11222685
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-11
[patent_title] => Refresh management for DRAM
[patent_app_type] => utility
[patent_app_number] => 16/875281
[patent_app_country] => US
[patent_app_date] => 2020-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6154
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875281
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/875281 | Refresh management for DRAM | May 14, 2020 | Issued |
Array
(
[id] => 17077724
[patent_doc_number] => 11114135
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-07
[patent_title] => Apparatus and methods to provide power management for memory devices
[patent_app_type] => utility
[patent_app_number] => 16/863973
[patent_app_country] => US
[patent_app_date] => 2020-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 10722
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863973
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/863973 | Apparatus and methods to provide power management for memory devices | Apr 29, 2020 | Issued |
Array
(
[id] => 17018205
[patent_doc_number] => 11087850
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-10
[patent_title] => Sensing in floating-source memory architecture
[patent_app_type] => utility
[patent_app_number] => 16/862389
[patent_app_country] => US
[patent_app_date] => 2020-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 47
[patent_no_of_words] => 10225
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862389
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/862389 | Sensing in floating-source memory architecture | Apr 28, 2020 | Issued |
Array
(
[id] => 17077731
[patent_doc_number] => 11114142
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-07
[patent_title] => Reference voltage training circuit and semiconductor apparatus including the same
[patent_app_type] => utility
[patent_app_number] => 16/862172
[patent_app_country] => US
[patent_app_date] => 2020-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2970
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862172
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/862172 | Reference voltage training circuit and semiconductor apparatus including the same | Apr 28, 2020 | Issued |
Array
(
[id] => 17152251
[patent_doc_number] => 11145338
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-12
[patent_title] => Semiconductor memory device and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 16/860867
[patent_app_country] => US
[patent_app_date] => 2020-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 9369
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860867
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/860867 | Semiconductor memory device and method of operating the same | Apr 27, 2020 | Issued |
Array
(
[id] => 17091230
[patent_doc_number] => 11119414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Yield estimation and control
[patent_app_type] => utility
[patent_app_number] => 16/851477
[patent_app_country] => US
[patent_app_date] => 2020-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 13592
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851477
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/851477 | Yield estimation and control | Apr 16, 2020 | Issued |
Array
(
[id] => 16347768
[patent_doc_number] => 20200312419
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => FIRST-PASS DYNAMIC PROGRAM TARGETING (DPT)
[patent_app_type] => utility
[patent_app_number] => 16/848267
[patent_app_country] => US
[patent_app_date] => 2020-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14981
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16848267
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/848267 | First-pass dynamic program targeting (DPT) | Apr 13, 2020 | Issued |
Array
(
[id] => 17239606
[patent_doc_number] => 11183498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-23
[patent_title] => Semiconductor memory device having an electrically floating body transistor
[patent_app_type] => utility
[patent_app_number] => 16/844715
[patent_app_country] => US
[patent_app_date] => 2020-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 147
[patent_figures_cnt] => 245
[patent_no_of_words] => 41821
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844715
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/844715 | Semiconductor memory device having an electrically floating body transistor | Apr 8, 2020 | Issued |
Array
(
[id] => 17144963
[patent_doc_number] => 20210312976
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-07
[patent_title] => READ REFRESH OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/842524
[patent_app_country] => US
[patent_app_date] => 2020-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19082
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842524
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/842524 | Read refresh operation | Apr 6, 2020 | Issued |
Array
(
[id] => 16765294
[patent_doc_number] => 20210110876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => SEMICONDUCTOR MEMORY DEVICE EMPLOYING PROCESSING IN MEMORY (PIM) AND OPERATION METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/833864
[patent_app_country] => US
[patent_app_date] => 2020-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10118
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833864
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/833864 | Semiconductor memory device employing processing in memory (PIM) and operation method of the semiconductor memory device | Mar 29, 2020 | Issued |
Array
(
[id] => 16928079
[patent_doc_number] => 11049568
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-06-29
[patent_title] => Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage
[patent_app_type] => utility
[patent_app_number] => 16/832320
[patent_app_country] => US
[patent_app_date] => 2020-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 42
[patent_no_of_words] => 23421
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832320
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/832320 | Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage | Mar 26, 2020 | Issued |
Array
(
[id] => 16180157
[patent_doc_number] => 20200227126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => Memory Device with a Fuse Protection Circuit
[patent_app_type] => utility
[patent_app_number] => 16/830429
[patent_app_country] => US
[patent_app_date] => 2020-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8075
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830429
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/830429 | Memory device with a fuse protection circuit | Mar 25, 2020 | Issued |
Array
(
[id] => 16631854
[patent_doc_number] => 20210050508
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => MAGNETIC MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/829216
[patent_app_country] => US
[patent_app_date] => 2020-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8620
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829216
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/829216 | Magnetic memory device | Mar 24, 2020 | Issued |
Array
(
[id] => 16455783
[patent_doc_number] => 20200365209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-19
[patent_title] => NEAR-MEMORY COMPUTATION SYSTEM FOR ANALOG COMPUTING
[patent_app_type] => utility
[patent_app_number] => 16/826278
[patent_app_country] => US
[patent_app_date] => 2020-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4173
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826278
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/826278 | Near-memory computation system for analog computing | Mar 21, 2020 | Issued |
Array
(
[id] => 16988031
[patent_doc_number] => 11075214
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-27
[patent_title] => NOR memory cell with vertical floating gate
[patent_app_type] => utility
[patent_app_number] => 16/825808
[patent_app_country] => US
[patent_app_date] => 2020-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 7725
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 275
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825808
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/825808 | NOR memory cell with vertical floating gate | Mar 19, 2020 | Issued |
Array
(
[id] => 17115301
[patent_doc_number] => 20210295898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => BITCELL WITH MULTIPLE READ BITLINES
[patent_app_type] => utility
[patent_app_number] => 16/824663
[patent_app_country] => US
[patent_app_date] => 2020-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7128
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824663
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/824663 | Bitcell with multiple read bitlines | Mar 18, 2020 | Issued |
Array
(
[id] => 17077763
[patent_doc_number] => 11114176
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-09-07
[patent_title] => Systems and methods to provide write termination for one time programmable memory cells
[patent_app_type] => utility
[patent_app_number] => 16/811145
[patent_app_country] => US
[patent_app_date] => 2020-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8322
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811145
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/811145 | Systems and methods to provide write termination for one time programmable memory cells | Mar 5, 2020 | Issued |
Array
(
[id] => 16759612
[patent_doc_number] => 10978167
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-04-13
[patent_title] => Efuse bank and associated anchor bits
[patent_app_type] => utility
[patent_app_number] => 16/806546
[patent_app_country] => US
[patent_app_date] => 2020-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4283
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806546
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/806546 | Efuse bank and associated anchor bits | Mar 1, 2020 | Issued |