Search

Huan Hoang

Examiner (ID: 18810, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2154, 2827, 2511
Total Applications
3293
Issued Applications
3069
Pending Applications
116
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15580865 [patent_doc_number] => 10580827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Adjustable stabilizer/polarizer method for MRAM with enhanced stability and efficient switching [patent_app_type] => utility [patent_app_number] => 16/192972 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 13928 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192972
Adjustable stabilizer/polarizer method for MRAM with enhanced stability and efficient switching Nov 15, 2018 Issued
Array ( [id] => 14903777 [patent_doc_number] => 20190295654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/192528 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192528 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192528
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE Nov 14, 2018 Abandoned
Array ( [id] => 14049327 [patent_doc_number] => 20190080770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => NON-VOLATILE MEMORY DEVICE INCLUDING DECOUPLING CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/186840 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186840
Non-volatile memory device including decoupling circuit Nov 11, 2018 Issued
Array ( [id] => 16356226 [patent_doc_number] => 10796743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Dynamic adjustment of memory cell digit line capacitance [patent_app_type] => utility [patent_app_number] => 16/184492 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184492 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184492
Dynamic adjustment of memory cell digit line capacitance Nov 7, 2018 Issued
Array ( [id] => 15857405 [patent_doc_number] => 10644001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Semiconductor memory device having an electrically floating body transistor [patent_app_type] => utility [patent_app_number] => 16/174377 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 147 [patent_figures_cnt] => 245 [patent_no_of_words] => 41793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174377
Semiconductor memory device having an electrically floating body transistor Oct 29, 2018 Issued
Array ( [id] => 15640763 [patent_doc_number] => 10593384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Methods of determining host clock frequency for run time optimization of memory and memory devices employing the same [patent_app_type] => utility [patent_app_number] => 16/174782 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2617 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174782 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174782
Methods of determining host clock frequency for run time optimization of memory and memory devices employing the same Oct 29, 2018 Issued
Array ( [id] => 16293275 [patent_doc_number] => 10770128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Non volatile mass storage device with improved refresh algorithm [patent_app_type] => utility [patent_app_number] => 16/147446 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5675 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147446 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147446
Non volatile mass storage device with improved refresh algorithm Sep 27, 2018 Issued
Array ( [id] => 15717107 [patent_doc_number] => 20200105321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => TECHNIQUE TO LOWER SWITCHING POWER OF BIT-LINES BY ADIABATIC CHARGING OF SRAM MEMORIES [patent_app_type] => utility [patent_app_number] => 16/147454 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147454
Technique to lower switching power of bit-lines by adiabatic charging of SRAM memories Sep 27, 2018 Issued
Array ( [id] => 13908761 [patent_doc_number] => 20190043585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => TAILORING TIMING OFFSETS DURING A PROGRAMMING PULSE FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/147422 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147422
Tailoring timing offsets during a programming pulse for a memory device Sep 27, 2018 Issued
Array ( [id] => 14858737 [patent_doc_number] => 10418102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Apparatuses and methods including memory and operation of same [patent_app_type] => utility [patent_app_number] => 16/137950 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7492 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137950
Apparatuses and methods including memory and operation of same Sep 20, 2018 Issued
Array ( [id] => 14858737 [patent_doc_number] => 10418102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Apparatuses and methods including memory and operation of same [patent_app_type] => utility [patent_app_number] => 16/137950 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7492 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137950
Apparatuses and methods including memory and operation of same Sep 20, 2018 Issued
Array ( [id] => 14858737 [patent_doc_number] => 10418102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Apparatuses and methods including memory and operation of same [patent_app_type] => utility [patent_app_number] => 16/137950 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7492 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137950
Apparatuses and methods including memory and operation of same Sep 20, 2018 Issued
Array ( [id] => 14858737 [patent_doc_number] => 10418102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Apparatuses and methods including memory and operation of same [patent_app_type] => utility [patent_app_number] => 16/137950 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7492 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137950
Apparatuses and methods including memory and operation of same Sep 20, 2018 Issued
Array ( [id] => 13832161 [patent_doc_number] => 20190019565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => Memory Device with a Fuse Protection Circuit [patent_app_type] => utility [patent_app_number] => 16/133783 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/133783
Memory device with a fuse protection circuit Sep 17, 2018 Issued
Array ( [id] => 13847983 [patent_doc_number] => 20190027476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => NAND String Utilizing Floating Body Memory Cell [patent_app_type] => utility [patent_app_number] => 16/132675 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132675
NAND string utilizing floating body memory cell Sep 16, 2018 Issued
Array ( [id] => 13799037 [patent_doc_number] => 20190013057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 16/131969 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16131969 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/131969
Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory Sep 13, 2018 Issued
Array ( [id] => 15657767 [patent_doc_number] => 20200091414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => MAGNETOELECTRIC SPIN ORBIT LOGIC BASED FULL ADDER [patent_app_type] => utility [patent_app_number] => 16/130912 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/130912
Magnetoelectric spin orbit logic based full adder Sep 12, 2018 Issued
Array ( [id] => 14237617 [patent_doc_number] => 20190130981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => DETECTING POWER LOSS IN NAND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/129497 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129497
Detecting power loss in NAND memory devices Sep 11, 2018 Issued
Array ( [id] => 15169501 [patent_doc_number] => 10490253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor system and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/129442 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5066 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129442
Semiconductor system and semiconductor device Sep 11, 2018 Issued
Array ( [id] => 16218235 [patent_doc_number] => 10734055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/128720 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128720 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128720
Memory device Sep 11, 2018 Issued
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