Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13613067 [patent_doc_number] => 20180358083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME [patent_app_type] => utility [patent_app_number] => 16/105631 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105631
Apparatuses and methods including two transistor-one capacitor memory and for accessing same Aug 19, 2018 Issued
Array ( [id] => 13613067 [patent_doc_number] => 20180358083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME [patent_app_type] => utility [patent_app_number] => 16/105631 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105631
Apparatuses and methods including two transistor-one capacitor memory and for accessing same Aug 19, 2018 Issued
Array ( [id] => 13613067 [patent_doc_number] => 20180358083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME [patent_app_type] => utility [patent_app_number] => 16/105631 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105631
Apparatuses and methods including two transistor-one capacitor memory and for accessing same Aug 19, 2018 Issued
Array ( [id] => 13613067 [patent_doc_number] => 20180358083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME [patent_app_type] => utility [patent_app_number] => 16/105631 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105631
Apparatuses and methods including two transistor-one capacitor memory and for accessing same Aug 19, 2018 Issued
Array ( [id] => 13613067 [patent_doc_number] => 20180358083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME [patent_app_type] => utility [patent_app_number] => 16/105631 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105631
Apparatuses and methods including two transistor-one capacitor memory and for accessing same Aug 19, 2018 Issued
Array ( [id] => 13908669 [patent_doc_number] => 20190043539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => APPARATUS AND METHODS TO PROVIDE POWER MANAGEMENT FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/102534 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102534
Apparatus and methods to provide power management for memory devices Aug 12, 2018 Issued
Array ( [id] => 15315021 [patent_doc_number] => 10522220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Phase change memory device with selector MOS transistors and source line clustering [patent_app_type] => utility [patent_app_number] => 16/056818 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056818
Phase change memory device with selector MOS transistors and source line clustering Aug 6, 2018 Issued
Array ( [id] => 14919969 [patent_doc_number] => 10431311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/056804 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056804
Semiconductor memory device Aug 6, 2018 Issued
Array ( [id] => 15488005 [patent_doc_number] => 10559357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-11 [patent_title] => Memory circuit having non-volatile memory cell and methods of using [patent_app_type] => utility [patent_app_number] => 16/056390 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056390 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056390
Memory circuit having non-volatile memory cell and methods of using Aug 5, 2018 Issued
Array ( [id] => 15060931 [patent_doc_number] => 10460777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Apparatuses and methods for providing constant DQS-DQ delay in a memory device [patent_app_type] => utility [patent_app_number] => 16/037546 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8872 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037546 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037546
Apparatuses and methods for providing constant DQS-DQ delay in a memory device Jul 16, 2018 Issued
Array ( [id] => 15199885 [patent_doc_number] => 10497444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance [patent_app_type] => utility [patent_app_number] => 16/037190 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037190 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037190
Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance Jul 16, 2018 Issued
Array ( [id] => 15703035 [patent_doc_number] => 10607704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Semiconductor memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/031552 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 10586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031552
Semiconductor memory device and method of operating the same Jul 9, 2018 Issued
Array ( [id] => 14381337 [patent_doc_number] => 20190164581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SENSE AMPLIFIER WITH COMPARISON NODE BIASING FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/031778 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031778 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031778
SENSE AMPLIFIER WITH COMPARISON NODE BIASING FOR NON-VOLATILE MEMORY Jul 9, 2018 Abandoned
Array ( [id] => 15672429 [patent_doc_number] => 10600452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Interconnection for memory electrodes [patent_app_type] => utility [patent_app_number] => 16/030584 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12575 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030584
Interconnection for memory electrodes Jul 8, 2018 Issued
Array ( [id] => 15199823 [patent_doc_number] => 10497412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Method and circuit for self-training of a reference voltage and memory system including the same [patent_app_type] => utility [patent_app_number] => 16/026286 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 18783 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026286
Method and circuit for self-training of a reference voltage and memory system including the same Jul 2, 2018 Issued
Array ( [id] => 14011215 [patent_doc_number] => 10224082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Semiconductor device and method of operation [patent_app_type] => utility [patent_app_number] => 16/010008 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5635 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16010008 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/010008
Semiconductor device and method of operation Jun 14, 2018 Issued
Array ( [id] => 15822595 [patent_doc_number] => 10636491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Flash memory device and method of programming the same [patent_app_type] => utility [patent_app_number] => 16/003848 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 12596 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/003848
Flash memory device and method of programming the same Jun 7, 2018 Issued
Array ( [id] => 15259695 [patent_doc_number] => 20190378581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR PROGRAM DISTURB INCLUDING SPIKE DURING BOOSTING [patent_app_type] => utility [patent_app_number] => 16/002836 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16002836 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/002836
Non-volatile memory with countermeasure for program disturb including spike during boosting Jun 6, 2018 Issued
Array ( [id] => 15108335 [patent_doc_number] => 10475497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Self-referenced sense amplifier with precharge [patent_app_type] => utility [patent_app_number] => 16/000071 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8769 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/000071
Self-referenced sense amplifier with precharge Jun 4, 2018 Issued
Array ( [id] => 15218231 [patent_doc_number] => 20190371802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => ANTI-FERROELECTRIC CAPACITOR MEMORY CELL [patent_app_type] => utility [patent_app_number] => 15/994227 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994227
Anti-ferroelectric capacitor memory cell May 30, 2018 Issued
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