Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13334445 [patent_doc_number] => 20180218760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => CONFIGURABLE STORAGE BLOCKS HAVING SIMPLE FIRST-IN FIRST-OUT ENABLING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 15/421090 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421090
Configurable storage blocks having simple first-in first-out enabling circuitry Jan 30, 2017 Issued
Array ( [id] => 12249185 [patent_doc_number] => 09921961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Multi-level memory management' [patent_app_type] => utility [patent_app_number] => 15/400122 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13198 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400122 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400122
Multi-level memory management Jan 5, 2017 Issued
Array ( [id] => 11983415 [patent_doc_number] => 20170287570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'ONE-TIME PROGRAMMABLE MEMORY DEVICE HAVING ACCESS CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/393838 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393838 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393838
One-time programmable memory device having access circuit Dec 28, 2016 Issued
Array ( [id] => 11760110 [patent_doc_number] => 20170206980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'METHOD FOR PROGRAMMING ANTIFUSE-TYPE ONE TIME PROGRAMMABLE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 15/392348 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7227 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392348 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/392348
Method for programming antifuse-type one time programmable memory cell Dec 27, 2016 Issued
Array ( [id] => 11557562 [patent_doc_number] => 20170103807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/389609 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8682 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389609 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389609
Nonvolatile semiconductor memory device Dec 22, 2016 Issued
Array ( [id] => 12168230 [patent_doc_number] => 09887000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-06 [patent_title] => 'System and method for cryogenic hybrid technology computing and memory' [patent_app_type] => utility [patent_app_number] => 15/374618 [patent_app_country] => US [patent_app_date] => 2016-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 52 [patent_no_of_words] => 18673 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15374618 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/374618
System and method for cryogenic hybrid technology computing and memory Dec 8, 2016 Issued
Array ( [id] => 11739982 [patent_doc_number] => 09704573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-11 [patent_title] => 'Three-transistor resistive random access memory cells' [patent_app_type] => utility [patent_app_number] => 15/375046 [patent_app_country] => US [patent_app_date] => 2016-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3948 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375046 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375046
Three-transistor resistive random access memory cells Dec 8, 2016 Issued
Array ( [id] => 12477222 [patent_doc_number] => 09990993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Three-transistor resistive random access memory cells [patent_app_type] => utility [patent_app_number] => 15/375036 [patent_app_country] => US [patent_app_date] => 2016-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4480 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375036 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375036
Three-transistor resistive random access memory cells Dec 8, 2016 Issued
Array ( [id] => 14011211 [patent_doc_number] => 10224080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Semiconductor memory device with late write feature [patent_app_type] => utility [patent_app_number] => 15/371062 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11867 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15371062 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/371062
Semiconductor memory device with late write feature Dec 5, 2016 Issued
Array ( [id] => 11939485 [patent_doc_number] => 20170243635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'Efficient Bitline Driven One-Sided Power Collapse Write-Assist Design For SRAMs' [patent_app_type] => utility [patent_app_number] => 15/367710 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5030 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367710
Efficient bitline driven one-sided power collapse write-assist design for SRAMs Dec 1, 2016 Issued
Array ( [id] => 11694157 [patent_doc_number] => 20170169875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'APPARATUSES AND METHODS FOR DYNAMIC VOLTAGE AND FREQUENCY SWITCHING FOR DYNAMIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 15/366198 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366198 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/366198
Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory Nov 30, 2016 Issued
Array ( [id] => 12553452 [patent_doc_number] => 10014039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Method and circuit for self-training of a reference voltage and memory system including the same [patent_app_type] => utility [patent_app_number] => 15/333468 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 18761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333468 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333468
Method and circuit for self-training of a reference voltage and memory system including the same Oct 24, 2016 Issued
Array ( [id] => 11592647 [patent_doc_number] => 20170117059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'EFUSE BIT CELL, AND READ/WRITE METHOD THEREOF, AND EFUSE ARRAY' [patent_app_type] => utility [patent_app_number] => 15/333894 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333894 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333894
Efuse bit cell, and read/write method thereof, and efuse array Oct 24, 2016 Issued
Array ( [id] => 12174633 [patent_doc_number] => 09892779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Memory device performing hammer refresh operation and memory system including the same' [patent_app_type] => utility [patent_app_number] => 15/331970 [patent_app_country] => US [patent_app_date] => 2016-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9976 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15331970 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/331970
Memory device performing hammer refresh operation and memory system including the same Oct 23, 2016 Issued
Array ( [id] => 14508891 [patent_doc_number] => 20190198100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => CONDUCTIVE BRIDGE RESISTIVE RANDOM ACCESS MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/329202 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16329202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/329202
CONDUCTIVE BRIDGE RESISTIVE RANDOM ACCESS MEMORY CELL Sep 29, 2016 Abandoned
Array ( [id] => 11532366 [patent_doc_number] => 20170092344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'DATA PROCESSING CIRCUIT FOR CONTROLLING SAMPLING POINT INDEPENDENTLY AND DATA PROCESSING SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/264946 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6635 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264946 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264946
Data processing circuit for controlling sampling point independently and data processing system including the same Sep 13, 2016 Issued
Array ( [id] => 11502583 [patent_doc_number] => 20170076768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'MEMORY DEVICE, MEMORY MODULE, AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/264774 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 18415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264774
Memory device, memory module, and memory system Sep 13, 2016 Issued
Array ( [id] => 11495197 [patent_doc_number] => 20170069382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'PATH ISOLATION IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/261301 [patent_app_country] => US [patent_app_date] => 2016-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6296 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261301 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/261301
Path isolation in a memory device Sep 8, 2016 Issued
Array ( [id] => 11966864 [patent_doc_number] => 20170271017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/258150 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/258150
Semiconductor memory device Sep 6, 2016 Issued
Array ( [id] => 11897943 [patent_doc_number] => 09767882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Method of refreshing memory device' [patent_app_type] => utility [patent_app_number] => 15/258174 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258174 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/258174
Method of refreshing memory device Sep 6, 2016 Issued
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