Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10999914 [patent_doc_number] => 20160196861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'MAGNETIC MEMORY AND SEMICONDUCTOR-INTEGRATED-CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/067586 [patent_app_country] => US [patent_app_date] => 2016-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067586
Magnetic memory and semiconductor-integrated-circuit Mar 10, 2016 Issued
Array ( [id] => 10992819 [patent_doc_number] => 20160189765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'Retention optimized memory device using predictive data inversion' [patent_app_type] => utility [patent_app_number] => 15/065378 [patent_app_country] => US [patent_app_date] => 2016-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 20352 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065378 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/065378
Retention optimized memory device using predictive data inversion Mar 8, 2016 Issued
Array ( [id] => 10992815 [patent_doc_number] => 20160189761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'MEMORY CONTROL CIRCUIT AND CACHE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/059842 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059842 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059842
Memory control circuit and cache memory Mar 2, 2016 Issued
Array ( [id] => 10983967 [patent_doc_number] => 20160180911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 15/057761 [patent_app_country] => US [patent_app_date] => 2016-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057761 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057761
Method of writing to a spin torque magnetic random access memory Feb 29, 2016 Issued
Array ( [id] => 10825851 [patent_doc_number] => 20160172019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'BOOSTED SUPPLY VOLTAGE GENERATOR FOR A MEMORY DEVICE AND METHOD THEREFORE' [patent_app_type] => utility [patent_app_number] => 15/051794 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051794 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051794
Boosted supply voltage generator for a memory device and method therefore Feb 23, 2016 Issued
Array ( [id] => 11069598 [patent_doc_number] => 20160266562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'NETWORK SYSTEM AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/051160 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7317 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051160 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051160
Network system and method for controlling the same Feb 22, 2016 Issued
Array ( [id] => 11049314 [patent_doc_number] => 20160246273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'CONTROLLER' [patent_app_type] => utility [patent_app_number] => 15/050632 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2434 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/050632
CONTROLLER Feb 22, 2016 Abandoned
Array ( [id] => 11615310 [patent_doc_number] => 09653172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Storage device and operating method thereof' [patent_app_type] => utility [patent_app_number] => 15/050946 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 12790 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050946 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/050946
Storage device and operating method thereof Feb 22, 2016 Issued
Array ( [id] => 11307398 [patent_doc_number] => 09514801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-06 [patent_title] => 'Semiconductor device generating a refresh signal' [patent_app_type] => utility [patent_app_number] => 15/041828 [patent_app_country] => US [patent_app_date] => 2016-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5943 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15041828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/041828
Semiconductor device generating a refresh signal Feb 10, 2016 Issued
Array ( [id] => 11239720 [patent_doc_number] => 09466365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Path isolation in a memory device' [patent_app_type] => utility [patent_app_number] => 15/018585 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6254 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018585 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/018585
Path isolation in a memory device Feb 7, 2016 Issued
Array ( [id] => 11681086 [patent_doc_number] => 09679621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Semiconductor device and semiconductor system' [patent_app_type] => utility [patent_app_number] => 15/017994 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7732 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15017994 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/017994
Semiconductor device and semiconductor system Feb 7, 2016 Issued
Array ( [id] => 14429831 [patent_doc_number] => 10319729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Methods and apparatuses with vertical strings of memory cells and support circuitry [patent_app_type] => utility [patent_app_number] => 15/011819 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 54 [patent_no_of_words] => 6630 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011819 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011819
Methods and apparatuses with vertical strings of memory cells and support circuitry Jan 31, 2016 Issued
Array ( [id] => 11005969 [patent_doc_number] => 20160202919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/990858 [patent_app_country] => US [patent_app_date] => 2016-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7621 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990858
Semiconductor device Jan 7, 2016 Issued
Array ( [id] => 10771985 [patent_doc_number] => 20160118141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'METHOD AND DEVICE FOR EVALUATING A CHIP MANUFACTURING PROCESS' [patent_app_type] => utility [patent_app_number] => 14/989822 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3072 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989822
Method and device for evaluating a chip manufacturing process Jan 6, 2016 Issued
Array ( [id] => 12313857 [patent_doc_number] => 09941004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Integrated arming switch and arming switch activation layer for secure memory [patent_app_type] => utility [patent_app_number] => 14/984426 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7134 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984426 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984426
Integrated arming switch and arming switch activation layer for secure memory Dec 29, 2015 Issued
Array ( [id] => 10787186 [patent_doc_number] => 20160133342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'INTEGRATED CIRCUIT HAVING VOLTAGE MISMATCH REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/980250 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980250
Integrated circuit having voltage mismatch reduction Dec 27, 2015 Issued
Array ( [id] => 10794867 [patent_doc_number] => 20160141024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ' [patent_app_type] => utility [patent_app_number] => 14/979458 [patent_app_country] => US [patent_app_date] => 2015-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 28565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979458 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979458
NAND array architecture for multiple simultaneous program and read Dec 26, 2015 Issued
Array ( [id] => 11207677 [patent_doc_number] => 09437306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'NAND array architecture for multiple simutaneous program and read' [patent_app_type] => utility [patent_app_number] => 14/979459 [patent_app_country] => US [patent_app_date] => 2015-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 28372 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979459 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979459
NAND array architecture for multiple simutaneous program and read Dec 26, 2015 Issued
Array ( [id] => 11644875 [patent_doc_number] => 09666263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'DIMM SSD SoC DRAM byte lane skewing' [patent_app_type] => utility [patent_app_number] => 14/973720 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5122 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973720 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973720
DIMM SSD SoC DRAM byte lane skewing Dec 16, 2015 Issued
Array ( [id] => 11259178 [patent_doc_number] => 09484081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Semiconductor device having transistor and semiconductor memory device using the same' [patent_app_type] => utility [patent_app_number] => 14/964031 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7030 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964031 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/964031
Semiconductor device having transistor and semiconductor memory device using the same Dec 8, 2015 Issued
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