Huan Hoang

Array ( [id] => 11207666 [patent_doc_number] => 09437295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Semiconductor system including semiconductor memory apparatus and temperature control method thereof' [patent_app_type] => utility [patent_app_number] => 14/956823 [patent_app_country] => US [patent_app_date] => 2015-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14956823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11524256 [patent_doc_number] => 09607666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Input/output circuit and input/output device including the same' [patent_app_type] => utility [patent_app_number] => 14/934570 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3980 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11607794 [patent_doc_number] => 20170125097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME' [patent_app_type] => utility [patent_app_number] => 14/932746 [patent_app_country] => US [patent_app_date] => 2015-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7784 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10710141 [patent_doc_number] => 20160056287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/930049 [patent_app_country] => US [patent_app_date] => 2015-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 148 [patent_figures_cnt] => 148 [patent_no_of_words] => 43987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14930049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11592641 [patent_doc_number] => 20170117053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SYSTEMS AND METHODS TO COMPENSATE FOR THRESHOLD VOLTAGE SHIFTS' [patent_app_type] => utility [patent_app_number] => 14/924339 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 17777 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11353465 [patent_doc_number] => 20160372205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SENSE AMPLIFIER DESIGN FOR RAMP SENSING' [patent_app_type] => utility [patent_app_number] => 14/924118 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12095674 [patent_doc_number] => 20170352767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'Electronic Memory Devices' [patent_app_type] => utility [patent_app_number] => 15/521208 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10033 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15521208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10763436 [patent_doc_number] => 20160109591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'NOISE MODEL ESTIMATION IN MULTIMEASUREMENT DATA' [patent_app_type] => utility [patent_app_number] => 14/882903 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11569929 [patent_doc_number] => 20170108572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'VOLTAGE PATTERN ANALYSIS SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/882778 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14248647 [patent_doc_number] => 10274520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Offset stacked compressor amplifiers in a discrete digitizer system for noise reduction and increased resolution [patent_app_type] => utility [patent_app_number] => 14/870357 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4913 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14870357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11516386 [patent_doc_number] => 20170083461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'INTEGRATED CIRCUIT WITH LOW LATENCY AND HIGH DENSITY ROUTING BETWEEN A MEMORY CONTROLLER DIGITAL CORE AND I/OS' [patent_app_type] => utility [patent_app_number] => 14/861114 [patent_app_country] => US [patent_app_date] => 2015-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3822 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14861114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10666755 [patent_doc_number] => 20160012900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/859110 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14725 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043288 [patent_doc_number] => 20160240244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'COLLISION DETECTION SYSTEMS FOR DETECTING READ-WRITE COLLISIONS IN MEMORY SYSTEMS AFTER WORD LINE ACTIVATION, AND RELATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/857512 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14857512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11088024 [patent_doc_number] => 20160284992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/856488 [patent_app_country] => US [patent_app_date] => 2015-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13121 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13157009 [patent_doc_number] => 10095225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Quality controlling device and control method thereof [patent_app_type] => utility [patent_app_number] => 14/854719 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7097 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10495075 [patent_doc_number] => 20150380098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'CONTINUOUS ADJUSTING OF SENSING VOLTAGES' [patent_app_type] => utility [patent_app_number] => 14/844722 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6640 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10624192 [patent_doc_number] => 09343140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Boosted read write word line' [patent_app_type] => utility [patent_app_number] => 14/844215 [patent_app_country] => US [patent_app_date] => 2015-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14844215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11475256 [patent_doc_number] => 20170062039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'MEMORY DEVICE THAT SUPPORTS MULTIPLE MEMORY CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 14/835986 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 14714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10495054 [patent_doc_number] => 20150380076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 14/835127 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10358 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11524590 [patent_doc_number] => 09608001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/833202 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5532 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833202 [rel_patent_id] =>[rel_patent_doc_number] =>)