Search

Huan Hoang

Examiner (ID: 18810, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2154, 2827, 2511
Total Applications
3293
Issued Applications
3069
Pending Applications
116
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19515441 [patent_doc_number] => 20240347127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => MEMORY DEVICE HEALTH MONITORING AND DYNAMIC ADJUSTMENT OF DEVICE PARAMETERS [patent_app_type] => utility [patent_app_number] => 18/627984 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627984
MEMORY DEVICE HEALTH MONITORING AND DYNAMIC ADJUSTMENT OF DEVICE PARAMETERS Apr 4, 2024 Pending
Array ( [id] => 20746641 [patent_doc_number] => 12646560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Data verification device and data verification method [patent_app_type] => utility [patent_app_number] => 18/624867 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624867
Data verification device and data verification method Apr 1, 2024 Issued
Array ( [id] => 20250842 [patent_doc_number] => 20250299711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => ALLOCATING THERMAL REGION TAGS IN A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/615141 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615141 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615141
ALLOCATING THERMAL REGION TAGS IN A STORAGE DEVICE Mar 24, 2024 Pending
Array ( [id] => 19531469 [patent_doc_number] => 20240355371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/607033 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607033 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607033
DATA PATH SIGNAL AMPLIFICATION IN COUPLED SEMICONDUCTOR SYSTEMS Mar 14, 2024 Pending
Array ( [id] => 20111246 [patent_doc_number] => 12361981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Using embedded switches for reducing capacitive loading on a memory system [patent_app_type] => utility [patent_app_number] => 18/602521 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602521 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602521
Using embedded switches for reducing capacitive loading on a memory system Mar 11, 2024 Issued
Array ( [id] => 19435741 [patent_doc_number] => 20240304239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => MEMORY DEVICE CONFIGURED TO PERFORM A SEARCH OPERATION [patent_app_type] => utility [patent_app_number] => 18/587935 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587935
Memory device configured to perform a search operation Feb 25, 2024 Issued
Array ( [id] => 19435726 [patent_doc_number] => 20240304224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => READING METHOD FOR A MEMORY [patent_app_type] => utility [patent_app_number] => 18/583568 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583568
Reading method for a memory Feb 20, 2024 Issued
Array ( [id] => 20182126 [patent_doc_number] => 20250266084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => NON-VOLATILE MEMORY WITH HYBRID ROUTING FOR SHARED WORD LINE SWITCHES [patent_app_type] => utility [patent_app_number] => 18/443663 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443663 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443663
Non-volatile memory with hybrid routing for shared word line switches Feb 15, 2024 Issued
Array ( [id] => 19906324 [patent_doc_number] => 12283336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => System for differentiated thermal throttling of memory and method of operating same [patent_app_type] => utility [patent_app_number] => 18/439982 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 34 [patent_no_of_words] => 14320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439982 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439982
System for differentiated thermal throttling of memory and method of operating same Feb 12, 2024 Issued
Array ( [id] => 19945601 [patent_doc_number] => 12317753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Magnetic memory using spin-orbit torque [patent_app_type] => utility [patent_app_number] => 18/438174 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438174
Magnetic memory using spin-orbit torque Feb 8, 2024 Issued
Array ( [id] => 20758839 [patent_doc_number] => 12651615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Temperature control for multiple die types in a common package [patent_app_type] => utility [patent_app_number] => 18/435741 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1122 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435741 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435741
Temperature control for multiple die types in a common package Feb 6, 2024 Issued
Array ( [id] => 19205859 [patent_doc_number] => 20240177758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => READING METHOD AND READING CIRCUIT OF FRAM [patent_app_type] => utility [patent_app_number] => 18/434848 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434848 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434848
READING METHOD AND READING CIRCUIT OF FRAM Feb 6, 2024 Pending
Array ( [id] => 19881221 [patent_doc_number] => 20250113478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => BIT LINE WITH NON-UNIFORM WIDTH IN A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 18/433641 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433641
BIT LINE WITH NON-UNIFORM WIDTH IN A MEMORY ARRAY Feb 5, 2024 Pending
Array ( [id] => 20611014 [patent_doc_number] => 12586618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Memory system and memory die [patent_app_type] => utility [patent_app_number] => 18/429466 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429466
Memory system and memory die Jan 31, 2024 Issued
Array ( [id] => 19452414 [patent_doc_number] => 20240312544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => EFUSE UNIT AND APPLICATION CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 18/426018 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426018
Efuse unit and application circuit thereof Jan 28, 2024 Issued
Array ( [id] => 19820687 [patent_doc_number] => 20250078894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/426087 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426087 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426087
Memory device and operation method thereof Jan 28, 2024 Issued
Array ( [id] => 19335333 [patent_doc_number] => 20240249763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => REFRESHING A MEMORY DEVICE USING REAL-TIME CLOCK INFORMATION [patent_app_type] => utility [patent_app_number] => 18/417818 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417818
Refreshing a memory device using real-time clock information Jan 18, 2024 Issued
Array ( [id] => 19175835 [patent_doc_number] => 20240161809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => ROW CLEAR FEATURES FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/416777 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416777
Row clear features for memory devices and associated methods and systems Jan 17, 2024 Issued
Array ( [id] => 19589364 [patent_doc_number] => 20240386921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => MEMORY MODULE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/413180 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413180
Memory module and electronic system including the same Jan 15, 2024 Issued
Array ( [id] => 20088570 [patent_doc_number] => 20250218506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => TIME MULTIPLEXING OF CLEANUP AND WRITE FOR SERIAL READ WRITE MEMORY [patent_app_type] => utility [patent_app_number] => 18/402137 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402137
TIME MULTIPLEXING OF CLEANUP AND WRITE FOR SERIAL READ WRITE MEMORY Jan 1, 2024 Pending
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