Huan Hoang

Array ( [id] => 19054462 [patent_doc_number] => 20240096431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/522564 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20441304 [patent_doc_number] => 12512144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Control circuit and semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/519679 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 3842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20038217 [patent_doc_number] => 20250176439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SOT MRAM INCLUDING MTJ AND SELECTOR LOCATED ON OPPOSITE SIDES OF SOT LAYER AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/520401 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19191138 [patent_doc_number] => 20240170051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DISTRIBUTED WRITE DRIVER FOR MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 18/515812 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20118220 [patent_doc_number] => 12367935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Acceleration of data queries in memory [patent_app_type] => utility [patent_app_number] => 18/514707 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2362 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20274668 [patent_doc_number] => 12444452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Memory physical layer interface, memory apparatus and method thereof [patent_app_type] => utility [patent_app_number] => 18/509318 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20507886 [patent_doc_number] => 12542168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Data storage device and data protection method thereof [patent_app_type] => utility [patent_app_number] => 18/389227 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19007469 [patent_doc_number] => 20240071540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => NON-VOLATILE MEMORY DEVICE INCLUDING SENSE AMPLIFIER AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/502580 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20581207 [patent_doc_number] => 12573461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Managing sense amplifier latch and data latch voltage to reduce standby current [patent_app_type] => utility [patent_app_number] => 18/387217 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18387217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19007399 [patent_doc_number] => 20240071470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/499449 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19116128 [patent_doc_number] => 20240127878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHODS FOR ROW HAMMER MITIGATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 18/384682 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20258812 [patent_doc_number] => 12431173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Memory package performing training operation using address-delay mapping and memory system including the same [patent_app_type] => utility [patent_app_number] => 18/494258 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 8026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18958664 [patent_doc_number] => 20240046991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/491966 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19640468 [patent_doc_number] => 12171093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => NAND string utilizing floating body memory cell [patent_app_type] => utility [patent_app_number] => 18/377794 [patent_app_country] => US [patent_app_date] => 2023-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 47 [patent_no_of_words] => 16909 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19205845 [patent_doc_number] => 20240177744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => APPARATUSES AND METHODS INCLUDING CIRCUITS IN GAP REGIONS OF A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 18/481855 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19100745 [patent_doc_number] => 20240119973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => MEMORY DEVICES PERFORMING OFFSET COMPENSATING OPERATION [patent_app_type] => utility [patent_app_number] => 18/477773 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19130624 [patent_doc_number] => 20240135977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => OPERATING METHOD OF MEMORY CONTROLLER, AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/473492 [patent_app_country] => US [patent_app_date] => 2023-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19130624 [patent_doc_number] => 20240135977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => OPERATING METHOD OF MEMORY CONTROLLER, AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/473492 [patent_app_country] => US [patent_app_date] => 2023-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19850353 [patent_doc_number] => 20250095704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => MEMORY DEVICE HAVING TRACKING WORD LINE WITH ADJUST CIRCUIT, METHOD OF OPERATING SAME AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/472132 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20161171 [patent_doc_number] => 12387804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Anti-fuse memory device [patent_app_type] => utility [patent_app_number] => 18/370404 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18370404 [rel_patent_id] =>[rel_patent_doc_number] =>)