Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10666750 [patent_doc_number] => 20160012895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/563350 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5918 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14563350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/563350
Semiconductor memory device, memory system having the same, and method of operating the same Dec 7, 2014 Issued
Array ( [id] => 10725414 [patent_doc_number] => 20160071562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'STACK TYPE SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/562992 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562992 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562992
Stack type semiconductor apparatus Dec 7, 2014 Issued
Array ( [id] => 11346095 [patent_doc_number] => 09530508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Memory device and method for operating the same' [patent_app_type] => utility [patent_app_number] => 14/558236 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3982 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14558236 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/558236
Memory device and method for operating the same Dec 1, 2014 Issued
Array ( [id] => 11227281 [patent_doc_number] => 09455007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Word line driver circuitry and compact memory using same' [patent_app_type] => utility [patent_app_number] => 14/556512 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14556512 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/556512
Word line driver circuitry and compact memory using same Nov 30, 2014 Issued
Array ( [id] => 10610726 [patent_doc_number] => 09330763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-03 [patent_title] => 'Operation modes for an inverted NAND architecture' [patent_app_type] => utility [patent_app_number] => 14/557004 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 15373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557004 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557004
Operation modes for an inverted NAND architecture Nov 30, 2014 Issued
Array ( [id] => 10802509 [patent_doc_number] => 20160148666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'MAGNETIC TUNNEL JUNCTION RESISTANCE COMPARISON BASED PHYSICAL UNCLONABLE FUNCTION' [patent_app_type] => utility [patent_app_number] => 14/555434 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7730 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555434 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555434
Magnetic tunnel junction resistance comparison based physical unclonable function Nov 25, 2014 Issued
Array ( [id] => 10802528 [patent_doc_number] => 20160148685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'RESISTIVE MEMORY WITH PROGRAM VERIFY AND ERASE VERIFY CAPABILITY' [patent_app_type] => utility [patent_app_number] => 14/554826 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554826 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554826
Resistive memory with program verify and erase verify capability Nov 25, 2014 Issued
Array ( [id] => 14668441 [patent_doc_number] => 10372119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Method for remote monitoring, and system for signal capturing and remote monitoring [patent_app_type] => utility [patent_app_number] => 14/554461 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5489 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554461
Method for remote monitoring, and system for signal capturing and remote monitoring Nov 25, 2014 Issued
Array ( [id] => 10264118 [patent_doc_number] => 20150149115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'Multi-function Padded Pants' [patent_app_type] => utility [patent_app_number] => 14/553189 [patent_app_country] => US [patent_app_date] => 2014-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14553189 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/553189
Multi-function Padded Pants Nov 24, 2014 Abandoned
Array ( [id] => 10800801 [patent_doc_number] => 20160146958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'Method and Computer System for Determining Seismic Node Position' [patent_app_type] => utility [patent_app_number] => 14/553172 [patent_app_country] => US [patent_app_date] => 2014-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5514 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14553172 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/553172
Method and computer system for determining seismic node position Nov 24, 2014 Issued
Array ( [id] => 10292274 [patent_doc_number] => 20150177274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'PRETREATMENT APPARATUS AND METHOD OF WHEEL SPEED' [patent_app_type] => utility [patent_app_number] => 14/553850 [patent_app_country] => US [patent_app_date] => 2014-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2811 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14553850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/553850
Pretreatment apparatus and method of wheel speed Nov 24, 2014 Issued
Array ( [id] => 10802544 [patent_doc_number] => 20160148701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/549532 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15275 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549532
Read level grouping algorithms for increased flash performance Nov 19, 2014 Issued
Array ( [id] => 10802544 [patent_doc_number] => 20160148701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/549532 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15275 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549532
Read level grouping algorithms for increased flash performance Nov 19, 2014 Issued
Array ( [id] => 10802544 [patent_doc_number] => 20160148701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/549532 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15275 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549532
Read level grouping algorithms for increased flash performance Nov 19, 2014 Issued
Array ( [id] => 10802544 [patent_doc_number] => 20160148701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/549532 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15275 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549532
Read level grouping algorithms for increased flash performance Nov 19, 2014 Issued
Array ( [id] => 11788146 [patent_doc_number] => 09397640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Latch circuit and semiconductor device including the same' [patent_app_type] => utility [patent_app_number] => 14/546760 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9108 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546760 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/546760
Latch circuit and semiconductor device including the same Nov 17, 2014 Issued
Array ( [id] => 10479180 [patent_doc_number] => 20150364197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/542920 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6182 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542920
Semiconductor memory device, memory system having the same and operating method thereof Nov 16, 2014 Issued
Array ( [id] => 11781612 [patent_doc_number] => 09390811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Semiconductor device with fuse array and method for operating the same' [patent_app_type] => utility [patent_app_number] => 14/543552 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543552
Semiconductor device with fuse array and method for operating the same Nov 16, 2014 Issued
Array ( [id] => 11770089 [patent_doc_number] => 09378774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Interconnection for memory electrodes' [patent_app_type] => utility [patent_app_number] => 14/543708 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12839 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543708 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543708
Interconnection for memory electrodes Nov 16, 2014 Issued
Array ( [id] => 11116677 [patent_doc_number] => 20160313651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'YIELD ESTIMATION AND CONTROL' [patent_app_type] => utility [patent_app_number] => 15/104517 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15104517 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/104517
Yield estimation and control Nov 13, 2014 Issued
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