
Huan Hoang
Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2154, 2827, 2511, 2818 |
| Total Applications | 3260 |
| Issued Applications | 3044 |
| Pending Applications | 110 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10590409
[patent_doc_number] => 09312029
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-12
[patent_title] => 'Memory device and associated controlling method'
[patent_app_type] => utility
[patent_app_number] => 14/309920
[patent_app_country] => US
[patent_app_date] => 2014-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 6794
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14309920
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/309920 | Memory device and associated controlling method | Jun 19, 2014 | Issued |
Array
(
[id] => 10973288
[patent_doc_number] => 20140376323
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-25
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/310722
[patent_app_country] => US
[patent_app_date] => 2014-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 10904
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310722
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/310722 | SEMICONDUCTOR DEVICE | Jun 19, 2014 | Abandoned |
Array
(
[id] => 10531055
[patent_doc_number] => 09257195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-09
[patent_title] => 'Memory controller operating method and memory system including memory controller'
[patent_app_type] => utility
[patent_app_number] => 14/309959
[patent_app_country] => US
[patent_app_date] => 2014-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 11883
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14309959
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/309959 | Memory controller operating method and memory system including memory controller | Jun 19, 2014 | Issued |
Array
(
[id] => 10846103
[patent_doc_number] => 08873293
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-28
[patent_title] => 'Dynamic erase voltage step size selection for 3D non-volatile memory'
[patent_app_type] => utility
[patent_app_number] => 14/279611
[patent_app_country] => US
[patent_app_date] => 2014-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 59
[patent_no_of_words] => 18318
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279611
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/279611 | Dynamic erase voltage step size selection for 3D non-volatile memory | May 15, 2014 | Issued |
Array
(
[id] => 10207502
[patent_doc_number] => 20150092491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/272512
[patent_app_country] => US
[patent_app_date] => 2014-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5837
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272512
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/272512 | Semiconductor memory device and erasing method | May 7, 2014 | Issued |
Array
(
[id] => 10512645
[patent_doc_number] => 09240223
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-19
[patent_title] => 'Semiconductor memory devices with a power supply'
[patent_app_type] => utility
[patent_app_number] => 14/272881
[patent_app_country] => US
[patent_app_date] => 2014-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 28
[patent_no_of_words] => 16259
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272881
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/272881 | Semiconductor memory devices with a power supply | May 7, 2014 | Issued |
Array
(
[id] => 10652359
[patent_doc_number] => 09368625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-14
[patent_title] => 'NAND string utilizing floating body memory cell'
[patent_app_type] => utility
[patent_app_number] => 14/267112
[patent_app_country] => US
[patent_app_date] => 2014-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 47
[patent_no_of_words] => 17317
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267112
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/267112 | NAND string utilizing floating body memory cell | Apr 30, 2014 | Issued |
Array
(
[id] => 9856427
[patent_doc_number] => 20150036444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-05
[patent_title] => 'SENSOR AMPLIFIER, MEMORY DEVICE COMPRISING SAME, AND RELATED METHOD OF OPERATION'
[patent_app_type] => utility
[patent_app_number] => 14/264466
[patent_app_country] => US
[patent_app_date] => 2014-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 10343
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264466
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/264466 | Sensor amplifier, memory device comprising same, and related method of operation | Apr 28, 2014 | Issued |
Array
(
[id] => 10610753
[patent_doc_number] => 09330790
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-03
[patent_title] => 'Temperature tracking to manage threshold voltages in a memory'
[patent_app_type] => utility
[patent_app_number] => 14/261560
[patent_app_country] => US
[patent_app_date] => 2014-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 5461
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261560
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/261560 | Temperature tracking to manage threshold voltages in a memory | Apr 24, 2014 | Issued |
Array
(
[id] => 9779661
[patent_doc_number] => 08854875
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-07
[patent_title] => 'Phase change memory with flexible time-based cell decoding'
[patent_app_type] => utility
[patent_app_number] => 14/242454
[patent_app_country] => US
[patent_app_date] => 2014-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 13726
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242454
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/242454 | Phase change memory with flexible time-based cell decoding | Mar 31, 2014 | Issued |
Array
(
[id] => 9614809
[patent_doc_number] => 20140204666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'Robust Initialization with Phase Change Memory Cells in Both Configuration and Array'
[patent_app_type] => utility
[patent_app_number] => 14/223268
[patent_app_country] => US
[patent_app_date] => 2014-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 9590
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223268
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/223268 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array | Mar 23, 2014 | Abandoned |
Array
(
[id] => 9614811
[patent_doc_number] => 20140204668
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'Robust Initialization with Phase Change Memory Cells in Both Configuration and Array'
[patent_app_type] => utility
[patent_app_number] => 14/223659
[patent_app_country] => US
[patent_app_date] => 2014-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 9591
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223659
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/223659 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array | Mar 23, 2014 | Abandoned |
Array
(
[id] => 9614810
[patent_doc_number] => 20140204667
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'Robust Initialization with Phase Change Memory Cells in Both Configuration and Array'
[patent_app_type] => utility
[patent_app_number] => 14/223636
[patent_app_country] => US
[patent_app_date] => 2014-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 9587
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223636
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/223636 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array | Mar 23, 2014 | Abandoned |
Array
(
[id] => 9614835
[patent_doc_number] => 20140204692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY'
[patent_app_type] => utility
[patent_app_number] => 14/220531
[patent_app_country] => US
[patent_app_date] => 2014-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7028
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14220531
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/220531 | Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality | Mar 19, 2014 | Issued |
Array
(
[id] => 10106484
[patent_doc_number] => 09142267
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-09-22
[patent_title] => 'Power generator for data line of memory apparatus'
[patent_app_type] => utility
[patent_app_number] => 14/215086
[patent_app_country] => US
[patent_app_date] => 2014-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3185
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14215086
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/215086 | Power generator for data line of memory apparatus | Mar 16, 2014 | Issued |
Array
(
[id] => 9915806
[patent_doc_number] => 20150071011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-12
[patent_title] => 'MEMORY DEVICE COMPRISING DOUBLE CASCODE SENSE AMPLIFIERS'
[patent_app_type] => utility
[patent_app_number] => 14/193708
[patent_app_country] => US
[patent_app_date] => 2014-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2115
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193708
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/193708 | Memory device comprising double cascode sense amplifiers | Feb 27, 2014 | Issued |
Array
(
[id] => 16323973
[patent_doc_number] => 10783943
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => MRAM having novel self-referenced read method
[patent_app_type] => utility
[patent_app_number] => 14/181880
[patent_app_country] => US
[patent_app_date] => 2014-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 5134
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14181880
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/181880 | MRAM having novel self-referenced read method | Feb 16, 2014 | Issued |
Array
(
[id] => 10200610
[patent_doc_number] => 20150085596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-26
[patent_title] => 'SEMICONDUCTOR DEVICES HAVING MULTI-CHANNEL REGIONS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/177382
[patent_app_country] => US
[patent_app_date] => 2014-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3933
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177382
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/177382 | Semiconductor devices having multi-channel regions and semiconductor systems including the same | Feb 10, 2014 | Issued |
Array
(
[id] => 10178630
[patent_doc_number] => 09208842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-08
[patent_title] => 'Method and system for operating memory'
[patent_app_type] => utility
[patent_app_number] => 14/162854
[patent_app_country] => US
[patent_app_date] => 2014-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2731
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162854
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/162854 | Method and system for operating memory | Jan 23, 2014 | Issued |
Array
(
[id] => 10525628
[patent_doc_number] => 09252148
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-02
[patent_title] => 'Methods and apparatuses with vertical strings of memory cells and support circuitry'
[patent_app_type] => utility
[patent_app_number] => 14/161170
[patent_app_country] => US
[patent_app_date] => 2014-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 54
[patent_no_of_words] => 6902
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161170
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/161170 | Methods and apparatuses with vertical strings of memory cells and support circuitry | Jan 21, 2014 | Issued |