Huan Hoang

Array ( [id] => 9434144 [patent_doc_number] => 20140112050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/051841 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 9378 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10383284 [patent_doc_number] => 20150268290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'Method for On-Line Diagnosing Gradually-Changing Fault of Electronic Current Transformers' [patent_app_type] => utility [patent_app_number] => 14/436815 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8574 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14436815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10408168 [patent_doc_number] => 20150293177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'METHOD FOR THE DIAGNOSTICS OF ELECTROMECHANICAL SYSTEM BASED ON IMPEDANCE ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/437864 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4159 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14437864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10178650 [patent_doc_number] => 09208861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Phase hysteretic magnetic Josephson junction memory cell' [patent_app_type] => utility [patent_app_number] => 14/043360 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043360 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9819351 [patent_doc_number] => 08929145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Nonvolatile memory device, programming method thereof and memory system including the same' [patent_app_type] => utility [patent_app_number] => 14/043256 [patent_app_country] => US [patent_app_date] => 2013-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 41 [patent_no_of_words] => 24216 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14043256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9859790 [patent_doc_number] => 20150039807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'NOR-TYPE FLASH MEMORY DEVICE CONFIGURED TO REDUCE PROGRAM MALFUNCTION' [patent_app_type] => utility [patent_app_number] => 14/041992 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3129 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10200588 [patent_doc_number] => 20150085574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'Back Gate Operation with Elevated Threshold Voltage' [patent_app_type] => utility [patent_app_number] => 14/033100 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9688 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10118415 [patent_doc_number] => 09153303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Methods and apparatuses for alternate clock selection' [patent_app_type] => utility [patent_app_number] => 14/031470 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3072 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14031470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9826582 [patent_doc_number] => RE045345 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2015-01-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => reissue [patent_app_number] => 14/032056 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 108 [patent_no_of_words] => 27502 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14032056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9221638 [patent_doc_number] => 20140016413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/029100 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 34930 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14029100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10865590 [patent_doc_number] => 08891308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-18 [patent_title] => 'Dynamic erase voltage step size selection for 3D non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/023920 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 59 [patent_no_of_words] => 18286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9678628 [patent_doc_number] => 08817548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Semiconductor memory device having an electrically floating body transistor' [patent_app_type] => utility [patent_app_number] => 14/018947 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 147 [patent_figures_cnt] => 245 [patent_no_of_words] => 43954 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10112068 [patent_doc_number] => 09147486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Continuous adjusting of sensing voltages' [patent_app_type] => utility [patent_app_number] => 14/018938 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6571 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10073227 [patent_doc_number] => 09111589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Memory timing circuit' [patent_app_type] => utility [patent_app_number] => 14/018404 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4536 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9907820 [patent_doc_number] => 20150063021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'MEMORY CONTROLLER FOR REDUCING CAPACITIVE COUPLING IN A CROSS-POINT MEMORY' [patent_app_type] => utility [patent_app_number] => 14/011476 [patent_app_country] => US [patent_app_date] => 2013-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14011476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9900233 [patent_doc_number] => 20150055431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'METHODS AND APPARATUSES INCLUDING TRANSMITTER CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/975128 [patent_app_country] => US [patent_app_date] => 2013-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5442 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13975128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9267932 [patent_doc_number] => 20140022848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-23 [patent_title] => 'NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/973218 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 23338 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13973218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9903464 [patent_doc_number] => 20150058664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'DYNAMIC MEMORY CELL REPLACEMENT USING COLUMN REDUNDANCY' [patent_app_type] => utility [patent_app_number] => 13/972082 [patent_app_country] => US [patent_app_date] => 2013-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10825868 [patent_doc_number] => 20160172036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/129676 [patent_app_country] => US [patent_app_date] => 2013-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7751 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14129676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9755382 [patent_doc_number] => 20140286084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'MAGNETORESISTIVE ELEMENT' [patent_app_type] => utility [patent_app_number] => 13/963654 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963654 [rel_patent_id] =>[rel_patent_doc_number] =>)