Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8459430 [patent_doc_number] => 08295106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Delay locked loop and method and electronic device including the same' [patent_app_type] => utility [patent_app_number] => 12/781800 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12781800 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781800
Delay locked loop and method and electronic device including the same May 16, 2010 Issued
Array ( [id] => 6123427 [patent_doc_number] => 20110085379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND SYSTEM AND RELATED METHOD OF OPERATION' [patent_app_type] => utility [patent_app_number] => 12/780988 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085379.pdf [firstpage_image] =>[orig_patent_app_number] => 12780988 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/780988
Nonvolatile memory device and system and related method of operation May 16, 2010 Issued
Array ( [id] => 7585558 [patent_doc_number] => 20110280068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/781774 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280068.pdf [firstpage_image] =>[orig_patent_app_number] => 12781774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781774
Joint encoding of logical pages in multi-page memory architecture May 16, 2010 Issued
Array ( [id] => 7585567 [patent_doc_number] => 20110280077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'MULTI-SEMICONDUCTOR MATERIAL VERTICAL MEMORY STRINGS, STRINGS OF MEMORY CELLS HAVING INDIVIDUALLY BIASABLE CHANNEL REGIONS, MEMORY ARRAYS INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/781346 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8614 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280077.pdf [firstpage_image] =>[orig_patent_app_number] => 12781346 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781346
Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accessing and forming the same May 16, 2010 Issued
Array ( [id] => 8117359 [patent_doc_number] => 08159899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Wordline driver for memory' [patent_app_type] => utility [patent_app_number] => 12/779752 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4114 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159899.pdf [firstpage_image] =>[orig_patent_app_number] => 12779752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/779752
Wordline driver for memory May 12, 2010 Issued
Array ( [id] => 6478430 [patent_doc_number] => 20100213528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING AN ARRAY STRUCTURE COMPRISING THE SAME DEVICES' [patent_app_type] => utility [patent_app_number] => 12/776204 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3564 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20100213528.pdf [firstpage_image] =>[orig_patent_app_number] => 12776204 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776204
METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING AN ARRAY STRUCTURE COMPRISING THE SAME DEVICES May 6, 2010 Abandoned
Array ( [id] => 5983211 [patent_doc_number] => 20110096583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'Semiconductor modules and signal line layout methods thereof' [patent_app_type] => utility [patent_app_number] => 12/662844 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20110096583.pdf [firstpage_image] =>[orig_patent_app_number] => 12662844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662844
Semiconductor modules and signal line layout methods thereof May 5, 2010 Issued
Array ( [id] => 7732250 [patent_doc_number] => 08102706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Programming a memory with varying bits per cell' [patent_app_type] => utility [patent_app_number] => 12/769713 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7044 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102706.pdf [firstpage_image] =>[orig_patent_app_number] => 12769713 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/769713
Programming a memory with varying bits per cell Apr 28, 2010 Issued
Array ( [id] => 8353535 [patent_doc_number] => 08248871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Redundancy circuits and semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 12/662644 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8053 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12662644 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662644
Redundancy circuits and semiconductor memory devices Apr 26, 2010 Issued
Array ( [id] => 6549988 [patent_doc_number] => 20100271895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities' [patent_app_type] => utility [patent_app_number] => 12/662564 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4815 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271895.pdf [firstpage_image] =>[orig_patent_app_number] => 12662564 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662564
SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities Apr 22, 2010 Issued
Array ( [id] => 8365087 [patent_doc_number] => 08254159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation' [patent_app_type] => utility [patent_app_number] => 12/662512 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8115 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12662512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662512
Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation Apr 20, 2010 Issued
Array ( [id] => 8117279 [patent_doc_number] => 08159861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Compact and highly efficient DRAM cell' [patent_app_type] => utility [patent_app_number] => 12/763780 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2698 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159861.pdf [firstpage_image] =>[orig_patent_app_number] => 12763780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763780
Compact and highly efficient DRAM cell Apr 19, 2010 Issued
Array ( [id] => 4620422 [patent_doc_number] => 08000146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Applying different body bias to different substrate portions for non-volatile storage' [patent_app_type] => utility [patent_app_number] => 12/759581 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 46 [patent_no_of_words] => 18938 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/000/08000146.pdf [firstpage_image] =>[orig_patent_app_number] => 12759581 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759581
Applying different body bias to different substrate portions for non-volatile storage Apr 12, 2010 Issued
Array ( [id] => 7980093 [patent_doc_number] => 08072799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/662029 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 10267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072799.pdf [firstpage_image] =>[orig_patent_app_number] => 12662029 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662029
Semiconductor integrated circuit device Mar 28, 2010 Issued
Array ( [id] => 8544905 [patent_doc_number] => 08320203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Method and system to lower the minimum operating voltage of register files' [patent_app_type] => utility [patent_app_number] => 12/748208 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12748208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748208
Method and system to lower the minimum operating voltage of register files Mar 25, 2010 Issued
Array ( [id] => 6331595 [patent_doc_number] => 20100246255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/729626 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7416 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20100246255.pdf [firstpage_image] =>[orig_patent_app_number] => 12729626 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729626
Nonvolatile semiconductor storage device and method for controlling the same Mar 22, 2010 Issued
Array ( [id] => 6421107 [patent_doc_number] => 20100142251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'MEMORY DEVICES HAVING PROGRAMMABLE ELEMENTS WITH ACCURATE OPERATING PARAMETERS STORED THEREON' [patent_app_type] => utility [patent_app_number] => 12/707491 [patent_app_country] => US [patent_app_date] => 2010-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20100142251.pdf [firstpage_image] =>[orig_patent_app_number] => 12707491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/707491
Memory devices having programmable elements with accurate operating parameters stored thereon Feb 16, 2010 Issued
Array ( [id] => 8471300 [patent_doc_number] => 08300488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh' [patent_app_type] => utility [patent_app_number] => 12/705040 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 20037 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12705040 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/705040
Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh Feb 11, 2010 Issued
Array ( [id] => 6421398 [patent_doc_number] => 20100142280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'PROGRAMMING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/703901 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20100142280.pdf [firstpage_image] =>[orig_patent_app_number] => 12703901 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703901
Programming memory devices Feb 10, 2010 Issued
Array ( [id] => 6564680 [patent_doc_number] => 20100128528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'MEMORY CELL PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 12/695559 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12083 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128528.pdf [firstpage_image] =>[orig_patent_app_number] => 12695559 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695559
Memory cell programming Jan 27, 2010 Issued
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