
Huan Hoang
Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2154, 2827, 2511, 2818 |
| Total Applications | 3260 |
| Issued Applications | 3044 |
| Pending Applications | 110 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8459430
[patent_doc_number] => 08295106
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[patent_kind] => B2
[patent_issue_date] => 2012-10-23
[patent_title] => 'Delay locked loop and method and electronic device including the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/781800 | Delay locked loop and method and electronic device including the same | May 16, 2010 | Issued |
Array
(
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[patent_doc_number] => 20110085379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-14
[patent_title] => 'NONVOLATILE MEMORY DEVICE AND SYSTEM AND RELATED METHOD OF OPERATION'
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Array
(
[id] => 7585558
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[patent_issue_date] => 2011-11-17
[patent_title] => 'JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/781774 | Joint encoding of logical pages in multi-page memory architecture | May 16, 2010 | Issued |
Array
(
[id] => 7585567
[patent_doc_number] => 20110280077
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[patent_kind] => A1
[patent_issue_date] => 2011-11-17
[patent_title] => 'MULTI-SEMICONDUCTOR MATERIAL VERTICAL MEMORY STRINGS, STRINGS OF MEMORY CELLS HAVING INDIVIDUALLY BIASABLE CHANNEL REGIONS, MEMORY ARRAYS INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/781346
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/781346 | Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accessing and forming the same | May 16, 2010 | Issued |
Array
(
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[patent_issue_date] => 2012-04-17
[patent_title] => 'Wordline driver for memory'
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Array
(
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Array
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[patent_doc_number] => 20110096583
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[patent_title] => 'Semiconductor modules and signal line layout methods thereof'
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Array
(
[id] => 7732250
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[patent_title] => 'Programming a memory with varying bits per cell'
[patent_app_type] => utility
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Array
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[id] => 8353535
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[patent_title] => 'Redundancy circuits and semiconductor memory devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/662644 | Redundancy circuits and semiconductor memory devices | Apr 26, 2010 | Issued |
Array
(
[id] => 6549988
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[patent_issue_date] => 2010-10-28
[patent_title] => 'SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities'
[patent_app_type] => utility
[patent_app_number] => 12/662564
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Array
(
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[patent_title] => 'Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation'
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Array
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[patent_title] => 'Compact and highly efficient DRAM cell'
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Array
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Array
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Array
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