Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 45016 [patent_doc_number] => 07782687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/252974 [patent_app_country] => US [patent_app_date] => 2008-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4232 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782687.pdf [firstpage_image] =>[orig_patent_app_number] => 12252974 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/252974
Semiconductor device Oct 15, 2008 Issued
Array ( [id] => 6470186 [patent_doc_number] => 20100091559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'Programmable resistance memory with feedback control' [patent_app_type] => utility [patent_app_number] => 12/287986 [patent_app_country] => US [patent_app_date] => 2008-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12532 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091559.pdf [firstpage_image] =>[orig_patent_app_number] => 12287986 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/287986
Programmable resistance memory with feedback control Oct 14, 2008 Issued
Array ( [id] => 279056 [patent_doc_number] => 07558138 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Bypass circuit for memory arrays' [patent_app_type] => utility [patent_app_number] => 12/242564 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1843 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558138.pdf [firstpage_image] =>[orig_patent_app_number] => 12242564 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242564
Bypass circuit for memory arrays Sep 29, 2008 Issued
Array ( [id] => 5519981 [patent_doc_number] => 20090027962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK' [patent_app_type] => utility [patent_app_number] => 12/240280 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3436 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027962.pdf [firstpage_image] =>[orig_patent_app_number] => 12240280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/240280
Multiple level cell memory device with single bit per cell, re-mappable memory block Sep 28, 2008 Issued
Array ( [id] => 5520001 [patent_doc_number] => 20090027982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'SEMICONDUCTOR MEMORY AND TEST SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/239052 [patent_app_country] => US [patent_app_date] => 2008-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027982.pdf [firstpage_image] =>[orig_patent_app_number] => 12239052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/239052
Semiconductor memory and test system Sep 25, 2008 Issued
Array ( [id] => 6361508 [patent_doc_number] => 20100074034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'VOLTAGE REGULATOR WITH REDUCED SENSITIVITY OF OUTPUT VOLTAGE TO CHANGE IN LOAD CURRENT' [patent_app_type] => utility [patent_app_number] => 12/236382 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9226 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20100074034.pdf [firstpage_image] =>[orig_patent_app_number] => 12236382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236382
Voltage regulator with reduced sensitivity of output voltage to change in load current Sep 22, 2008 Issued
Array ( [id] => 5308840 [patent_doc_number] => 20090016121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/233278 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4638 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016121.pdf [firstpage_image] =>[orig_patent_app_number] => 12233278 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233278
Semiconductor memory device and test method thereof Sep 17, 2008 Issued
Array ( [id] => 5520005 [patent_doc_number] => 20090027986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/232369 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6412 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027986.pdf [firstpage_image] =>[orig_patent_app_number] => 12232369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/232369
Semiconductor memory device Sep 15, 2008 Issued
Array ( [id] => 125580 [patent_doc_number] => 07706207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Memory with level shifting word line driver and method thereof' [patent_app_type] => utility [patent_app_number] => 12/209477 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4908 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706207.pdf [firstpage_image] =>[orig_patent_app_number] => 12209477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209477
Memory with level shifting word line driver and method thereof Sep 11, 2008 Issued
Array ( [id] => 6619707 [patent_doc_number] => 20100064114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'STACKED DEVICE IDENTIFICATION ASSIGNMENT' [patent_app_type] => utility [patent_app_number] => 12/209048 [patent_app_country] => US [patent_app_date] => 2008-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9426 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064114.pdf [firstpage_image] =>[orig_patent_app_number] => 12209048 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209048
Stacked device identification assignment Sep 10, 2008 Issued
Array ( [id] => 6587852 [patent_doc_number] => 20100321978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY CELL VOLTAGE APPLICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/747290 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20100321978.pdf [firstpage_image] =>[orig_patent_app_number] => 12747290 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/747290
Semiconductor memory device and memory cell voltage application method Sep 8, 2008 Issued
Array ( [id] => 7697974 [patent_doc_number] => 20110228616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency' [patent_app_type] => utility [patent_app_number] => 12/674598 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3720 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228616.pdf [firstpage_image] =>[orig_patent_app_number] => 12674598 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/674598
Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency Aug 21, 2008 Issued
Array ( [id] => 8271720 [patent_doc_number] => 08213229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Error control in a flash memory device' [patent_app_type] => utility [patent_app_number] => 12/196758 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5969 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12196758 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/196758
Error control in a flash memory device Aug 21, 2008 Issued
Array ( [id] => 5347677 [patent_doc_number] => 20090003038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Capacitor supported precharching of memory digit lines' [patent_app_type] => utility [patent_app_number] => 12/228459 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3328 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20090003038.pdf [firstpage_image] =>[orig_patent_app_number] => 12228459 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/228459
Capacitor supported precharging of memory digit lines Aug 11, 2008 Issued
Array ( [id] => 7560088 [patent_doc_number] => 20110273920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'SWITCHING ELEMENT AND APPLICATION OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/672151 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7019 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20110273920.pdf [firstpage_image] =>[orig_patent_app_number] => 12672151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/672151
Switching element and application of the same Aug 7, 2008 Issued
Array ( [id] => 7566200 [patent_doc_number] => 20110286263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/672238 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9628 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20110286263.pdf [firstpage_image] =>[orig_patent_app_number] => 12672238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/672238
Memory device Aug 4, 2008 Issued
Array ( [id] => 6508003 [patent_doc_number] => 20100202178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'OFFSET REMOVAL CIRCUIT, ASSOCIATIVE MEMORY INCLUDING THE SAME, AND OFFSET VOLTAGE REMOVAL METHOD' [patent_app_type] => utility [patent_app_number] => 12/665316 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8549 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202178.pdf [firstpage_image] =>[orig_patent_app_number] => 12665316 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/665316
Offset removal circuit, associative memory including the same, and offset voltage removal method Jul 30, 2008 Issued
Array ( [id] => 4584775 [patent_doc_number] => 07826304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Simplified power-down mode control circuit utilizing active mode operation control signals' [patent_app_type] => utility [patent_app_number] => 12/181426 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7721 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826304.pdf [firstpage_image] =>[orig_patent_app_number] => 12181426 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181426
Simplified power-down mode control circuit utilizing active mode operation control signals Jul 28, 2008 Issued
Array ( [id] => 76586 [patent_doc_number] => 07751246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Charge loss compensation during programming of a memory device' [patent_app_type] => utility [patent_app_number] => 12/177972 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4397 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/751/07751246.pdf [firstpage_image] =>[orig_patent_app_number] => 12177972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177972
Charge loss compensation during programming of a memory device Jul 22, 2008 Issued
Array ( [id] => 4958948 [patent_doc_number] => 20080273372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Method of Programming Multi-Layer Chalcogenide Devices' [patent_app_type] => utility [patent_app_number] => 12/178148 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15676 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273372.pdf [firstpage_image] =>[orig_patent_app_number] => 12178148 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/178148
Method of programming multi-layer chalcogenide devices Jul 22, 2008 Issued
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