Search

Huan Hoang

Examiner (ID: 18810, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2154, 2827, 2511
Total Applications
3293
Issued Applications
3069
Pending Applications
116
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19348879 [patent_doc_number] => 20240257843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/230951 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230951
Memory device and operating method thereof Aug 6, 2023 Issued
Array ( [id] => 18820819 [patent_doc_number] => 20230395160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => FLOATING DATA LINE CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/362549 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362549
Floating data line circuit and method Jul 30, 2023 Issued
Array ( [id] => 18789028 [patent_doc_number] => 20230377636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY CELL AND SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/228447 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228447
Semiconductor element memory cell and semiconductor element memory device Jul 30, 2023 Issued
Array ( [id] => 19552755 [patent_doc_number] => 12136466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Header layout design including backside power rail [patent_app_type] => utility [patent_app_number] => 18/362270 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362270 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362270
Header layout design including backside power rail Jul 30, 2023 Issued
Array ( [id] => 19370318 [patent_doc_number] => 12062408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Switches to reduce routing rails of memory system [patent_app_type] => utility [patent_app_number] => 18/361542 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8387 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361542
Switches to reduce routing rails of memory system Jul 27, 2023 Issued
Array ( [id] => 19749198 [patent_doc_number] => 20250037763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => TRANSIMPEDANCE AMPLIFIERS FOR CROSSBAR CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/361306 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361306 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361306
Transimpedance amplifiers for crossbar circuits Jul 27, 2023 Issued
Array ( [id] => 19749188 [patent_doc_number] => 20250037753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Memory with One-Transistor-Based Bit Line Tracking Circuit [patent_app_type] => utility [patent_app_number] => 18/360745 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360745 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360745
Memory with one-transistor-based bit line tracking circuit Jul 26, 2023 Issued
Array ( [id] => 19205850 [patent_doc_number] => 20240177749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY DEVICE AND SYSTEM DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/354869 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354869
Memory device and system device including the same Jul 18, 2023 Issued
Array ( [id] => 19483707 [patent_doc_number] => 20240331749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY, OPERATION METHOD OF MEMORY, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/222836 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/222836
Memory, operation method of memory, and memory system Jul 16, 2023 Issued
Array ( [id] => 20404265 [patent_doc_number] => 12494245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Word line-dependent word line and channel read setup time in first read state of non-volatile memory [patent_app_type] => utility [patent_app_number] => 18/222708 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 13645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/222708
Word line-dependent word line and channel read setup time in first read state of non-volatile memory Jul 16, 2023 Issued
Array ( [id] => 18743072 [patent_doc_number] => 20230352060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => CIRCUIT MODULE WITH IMPROVED LINE LOAD [patent_app_type] => utility [patent_app_number] => 18/221111 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221111
Circuit module with improved line load Jul 11, 2023 Issued
Array ( [id] => 19712352 [patent_doc_number] => 20250022494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => High-Speed and Area-Efficient Parallel-Write-and-Read Memory [patent_app_type] => utility [patent_app_number] => 18/349918 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349918
High-speed and area-efficient parallel-write-and-read memory Jul 9, 2023 Issued
Array ( [id] => 19696080 [patent_doc_number] => 20250014625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => FERROELECTRIC MEMORY REFERENCE GENERATION [patent_app_type] => utility [patent_app_number] => 18/219439 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219439
Ferroelectric memory reference generation Jul 6, 2023 Issued
Array ( [id] => 18731392 [patent_doc_number] => 20230345700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Semiconductor Memory Device Having an Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 18/216359 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216359
Semiconductor memory device having an electrically floating body transistor Jun 28, 2023 Issued
Array ( [id] => 20429353 [patent_doc_number] => 20250391446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => VOLTAGE MANAGEMENT CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/878525 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18878525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/878525
VOLTAGE MANAGEMENT CIRCUIT Jun 20, 2023 Pending
Array ( [id] => 19500123 [patent_doc_number] => 20240339141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Tracking Circuitry and Memory Devices Including the Same [patent_app_type] => utility [patent_app_number] => 18/333592 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333592 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333592
Tracking circuitry and memory devices including the same Jun 12, 2023 Issued
Array ( [id] => 20405730 [patent_doc_number] => 12495721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Semiconductor device with asymmetrical pinned magnets, and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/333397 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 2266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333397
Semiconductor device with asymmetrical pinned magnets, and method of manufacture Jun 11, 2023 Issued
Array ( [id] => 19146003 [patent_doc_number] => 20240145019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => POWER SOURCE SWITCHING CIRCUIT FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/330768 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330768
Power source switching circuit for memory device Jun 6, 2023 Issued
Array ( [id] => 20538540 [patent_doc_number] => 12555619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Preamble detection circuit, operation method thereof, and memory device [patent_app_type] => utility [patent_app_number] => 18/325443 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 2273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325443
Preamble detection circuit, operation method thereof, and memory device May 29, 2023 Issued
Array ( [id] => 20243939 [patent_doc_number] => 12424269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Semiconductor memory device capable of adaptively controlling bias and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/199114 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3528 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199114
Semiconductor memory device capable of adaptively controlling bias and method of operating the same May 17, 2023 Issued
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