Huan Hoang

Array ( [id] => 5551020 [patent_doc_number] => 20090285006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Semiconductor Memory and Method for Operating a Semiconductor Memory' [patent_app_type] => utility [patent_app_number] => 12/125684 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7694 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20090285006.pdf [firstpage_image] =>[orig_patent_app_number] => 12125684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 353605 [patent_doc_number] => 07492631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Methods involving resetting spin-torque magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 12/118496 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2020 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/492/07492631.pdf [firstpage_image] =>[orig_patent_app_number] => 12118496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 35070 [patent_doc_number] => 07791977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Design structure for low overhead switched header power savings apparatus' [patent_app_type] => utility [patent_app_number] => 12/116322 [patent_app_country] => US [patent_app_date] => 2008-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5608 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791977.pdf [firstpage_image] =>[orig_patent_app_number] => 12116322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5313993 [patent_doc_number] => 20090278591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'POWER SUPPLIES IN FLASH MEMORY DEVICES AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/115784 [patent_app_country] => US [patent_app_date] => 2008-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5868 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20090278591.pdf [firstpage_image] =>[orig_patent_app_number] => 12115784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5484233 [patent_doc_number] => 20090273998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/114966 [patent_app_country] => US [patent_app_date] => 2008-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6386 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273998.pdf [firstpage_image] =>[orig_patent_app_number] => 12114966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 56357 [patent_doc_number] => 07768850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'System for bitcell and column testing in SRAM' [patent_app_type] => utility [patent_app_number] => 12/115122 [patent_app_country] => US [patent_app_date] => 2008-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3732 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768850.pdf [firstpage_image] =>[orig_patent_app_number] => 12115122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4506963 [patent_doc_number] => 07920423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-05 [patent_title] => 'Non volatile memory circuit with tailored reliability' [patent_app_type] => utility [patent_app_number] => 12/114574 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 5073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/920/07920423.pdf [firstpage_image] =>[orig_patent_app_number] => 12114574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7797119 [patent_doc_number] => 08125829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Biasing system and method' [patent_app_type] => utility [patent_app_number] => 12/114570 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 8696 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/125/08125829.pdf [firstpage_image] =>[orig_patent_app_number] => 12114570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5463183 [patent_doc_number] => 20090323383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'COMPARING DATA REPRESENTATIONS TO STORED PATTERNS' [patent_app_type] => utility [patent_app_number] => 12/107636 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6375 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20090323383.pdf [firstpage_image] =>[orig_patent_app_number] => 12107636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5377428 [patent_doc_number] => 20090189267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'SEMICONDUCTOR CHIP WITH CHIP SELECTION STRUCTURE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/059308 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6814 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189267.pdf [firstpage_image] =>[orig_patent_app_number] => 12059308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 154469 [patent_doc_number] => 07679970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Semiconductor memory device for simultaneously performing read access and write access' [patent_app_type] => utility [patent_app_number] => 12/059080 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3951 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679970.pdf [firstpage_image] =>[orig_patent_app_number] => 12059080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 187175 [patent_doc_number] => 07646668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Maintaining dynamic count of FIFO contents in multiple clock domains' [patent_app_type] => utility [patent_app_number] => 12/058964 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3144 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646668.pdf [firstpage_image] =>[orig_patent_app_number] => 12058964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4858078 [patent_doc_number] => 20080266928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/059220 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11012 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266928.pdf [firstpage_image] =>[orig_patent_app_number] => 12059220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4584631 [patent_doc_number] => 07826280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Integrated circuit and method for reading the content of a memory cell' [patent_app_type] => utility [patent_app_number] => 12/057746 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9930 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826280.pdf [firstpage_image] =>[orig_patent_app_number] => 12057746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 186783 [patent_doc_number] => 07649776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Nonvolatile semiconductor memory system' [patent_app_type] => utility [patent_app_number] => 12/058356 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 21775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649776.pdf [firstpage_image] =>[orig_patent_app_number] => 12058356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5421152 [patent_doc_number] => 20090147607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'RANDOM ACCESS MEMORY AND DATA REFRESHING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/056278 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2153 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20090147607.pdf [firstpage_image] =>[orig_patent_app_number] => 12056278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 229829 [patent_doc_number] => 07602646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-13 [patent_title] => 'Threshold evaluation of EPROM cells' [patent_app_type] => utility [patent_app_number] => 12/056570 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5138 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602646.pdf [firstpage_image] =>[orig_patent_app_number] => 12056570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 115546 [patent_doc_number] => 07715241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Method for erasing a P-channel non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/056288 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3894 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/715/07715241.pdf [firstpage_image] =>[orig_patent_app_number] => 12056288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16052 [patent_doc_number] => 07808834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'Incremental memory refresh' [patent_app_type] => utility [patent_app_number] => 12/055470 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 11471 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808834.pdf [firstpage_image] =>[orig_patent_app_number] => 12055470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4806847 [patent_doc_number] => 20080170425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'METHODS AND APPARATUS OF STACKING DRAMS' [patent_app_type] => utility [patent_app_number] => 12/055107 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14373 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170425.pdf [firstpage_image] =>[orig_patent_app_number] => 12055107 [rel_patent_id] =>[rel_patent_doc_number] =>)