Huan Hoang

Array ( [id] => 5402688 [patent_doc_number] => 20090238002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'NAND TYPE NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/053636 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5198 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20090238002.pdf [firstpage_image] =>[orig_patent_app_number] => 12053636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5402683 [patent_doc_number] => 20090237997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/053976 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3480 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237997.pdf [firstpage_image] =>[orig_patent_app_number] => 12053976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5402670 [patent_doc_number] => 20090237984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/053236 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7702 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237984.pdf [firstpage_image] =>[orig_patent_app_number] => 12053236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 312105 [patent_doc_number] => 07529141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Asynchronous, high-bandwidth memory component using calibrated timing elements' [patent_app_type] => utility [patent_app_number] => 12/041594 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 38 [patent_no_of_words] => 20511 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529141.pdf [firstpage_image] =>[orig_patent_app_number] => 12041594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4674741 [patent_doc_number] => 20080212369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'METHOD OF MANAGING A MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS' [patent_app_type] => utility [patent_app_number] => 12/039268 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2600 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20080212369.pdf [firstpage_image] =>[orig_patent_app_number] => 12039268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6348384 [patent_doc_number] => 20100085790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'AMPLIFIER CIRCUIT AND ASSOCIATIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/528776 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4800 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085790.pdf [firstpage_image] =>[orig_patent_app_number] => 12528776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 26193 [patent_doc_number] => 07796450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Radio frequency (RFID) tag including configurable single bit/dual bits memory' [patent_app_type] => utility [patent_app_number] => 12/012910 [patent_app_country] => US [patent_app_date] => 2008-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3810 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/796/07796450.pdf [firstpage_image] =>[orig_patent_app_number] => 12012910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4831827 [patent_doc_number] => 20080130373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'PROGRAMMING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/025815 [patent_app_country] => US [patent_app_date] => 2008-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3833 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20080130373.pdf [firstpage_image] =>[orig_patent_app_number] => 12025815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 248028 [patent_doc_number] => 07586785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/020981 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 11913 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/586/07586785.pdf [firstpage_image] =>[orig_patent_app_number] => 12020981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5579720 [patent_doc_number] => 20090175066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'High-speed DRAM including hierarchical read circuits' [patent_app_type] => utility [patent_app_number] => 11/971108 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20090175066.pdf [firstpage_image] =>[orig_patent_app_number] => 11971108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 327723 [patent_doc_number] => 07515504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Phase controlled high speed interfaces' [patent_app_type] => utility [patent_app_number] => 11/969404 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5676 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/515/07515504.pdf [firstpage_image] =>[orig_patent_app_number] => 11969404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 186762 [patent_doc_number] => 07649765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Magnetic memory cell and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 11/964359 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 49 [patent_no_of_words] => 4265 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649765.pdf [firstpage_image] =>[orig_patent_app_number] => 11964359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4584603 [patent_doc_number] => 07826276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Non-volatile memory device reducing data programming and verification time, and method of driving the same' [patent_app_type] => utility [patent_app_number] => 12/003381 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826276.pdf [firstpage_image] =>[orig_patent_app_number] => 12003381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4784065 [patent_doc_number] => 20080137394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/000343 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 34978 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20080137394.pdf [firstpage_image] =>[orig_patent_app_number] => 12000343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 818354 [patent_doc_number] => 07411827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Boosting to control programming of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/945203 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 15927 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411827.pdf [firstpage_image] =>[orig_patent_app_number] => 11945203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4920580 [patent_doc_number] => 20080068894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'DIFFERENTIAL FLASH MEMORY PROGRAMMING TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 11/943502 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1927 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20080068894.pdf [firstpage_image] =>[orig_patent_app_number] => 11943502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 831082 [patent_doc_number] => 07400546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-15 [patent_title] => 'Low overhead switched header power savings apparatus' [patent_app_type] => utility [patent_app_number] => 11/940642 [patent_app_country] => US [patent_app_date] => 2007-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4948 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/400/07400546.pdf [firstpage_image] =>[orig_patent_app_number] => 11940642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7590405 [patent_doc_number] => 07663954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Semiconductor memory device including a sense amplifier having a reduced operating current' [patent_app_type] => utility [patent_app_number] => 11/979954 [patent_app_country] => US [patent_app_date] => 2007-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8655 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663954.pdf [firstpage_image] =>[orig_patent_app_number] => 11979954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4953771 [patent_doc_number] => 20080186795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Elastic Power for Read Margins' [patent_app_type] => utility [patent_app_number] => 11/938196 [patent_app_country] => US [patent_app_date] => 2007-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4926 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186795.pdf [firstpage_image] =>[orig_patent_app_number] => 11938196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15980 [patent_doc_number] => 07808804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Power line layout' [patent_app_type] => utility [patent_app_number] => 11/979868 [patent_app_country] => US [patent_app_date] => 2007-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808804.pdf [firstpage_image] =>[orig_patent_app_number] => 11979868 [rel_patent_id] =>[rel_patent_doc_number] =>)