Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4645701 [patent_doc_number] => 08023312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/515286 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 108 [patent_no_of_words] => 27496 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 557 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/023/08023312.pdf [firstpage_image] =>[orig_patent_app_number] => 12515286 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/515286
Nonvolatile semiconductor memory device Nov 4, 2007 Issued
Array ( [id] => 144556 [patent_doc_number] => 07692998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Circuit of detecting power-up and power-down' [patent_app_type] => utility [patent_app_number] => 11/979424 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7357 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/692/07692998.pdf [firstpage_image] =>[orig_patent_app_number] => 11979424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/979424
Circuit of detecting power-up and power-down Nov 1, 2007 Issued
Array ( [id] => 237040 [patent_doc_number] => 07596023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Memory device employing three-level cells and related methods of managing' [patent_app_type] => utility [patent_app_number] => 11/934144 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 5784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596023.pdf [firstpage_image] =>[orig_patent_app_number] => 11934144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934144
Memory device employing three-level cells and related methods of managing Nov 1, 2007 Issued
Array ( [id] => 4964110 [patent_doc_number] => 20080106930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'PRAM AND METHOD OF FIRING MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 11/933536 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5565 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20080106930.pdf [firstpage_image] =>[orig_patent_app_number] => 11933536 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933536
PRAM and method of firing memory cells Oct 31, 2007 Issued
Array ( [id] => 4964127 [patent_doc_number] => 20080106947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'DECODERS AND DECODING METHODS FOR NONVOLATILE MEMORY DEVICES USING LEVEL SHIFTING' [patent_app_type] => utility [patent_app_number] => 11/933716 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20080106947.pdf [firstpage_image] =>[orig_patent_app_number] => 11933716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933716
Decoders and decoding methods for nonvolatile memory devices using level shifting Oct 31, 2007 Issued
Array ( [id] => 4964121 [patent_doc_number] => 20080106941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'DECODERS AND DECODING METHODS FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/933702 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4994 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20080106941.pdf [firstpage_image] =>[orig_patent_app_number] => 11933702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933702
Decoders and decoding methods for nonvolatile semiconductor memory devices Oct 31, 2007 Issued
Array ( [id] => 7594610 [patent_doc_number] => 07626853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-01 [patent_title] => 'Method of operating memory cell providing internal power switching' [patent_app_type] => utility [patent_app_number] => 11/932738 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6356 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626853.pdf [firstpage_image] =>[orig_patent_app_number] => 11932738 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932738
Method of operating memory cell providing internal power switching Oct 30, 2007 Issued
Array ( [id] => 5329256 [patent_doc_number] => 20090109733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Design structure for sram active write assist for improved operational margins' [patent_app_type] => utility [patent_app_number] => 11/981882 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8345 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109733.pdf [firstpage_image] =>[orig_patent_app_number] => 11981882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981882
Design structure for SRAM active write assist for improved operational margins Oct 30, 2007 Issued
Array ( [id] => 5329268 [patent_doc_number] => 20090109745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'NON-VOLATILE MULTILEVEL MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 11/931912 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9121 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109745.pdf [firstpage_image] =>[orig_patent_app_number] => 11931912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/931912
Non-volatile multilevel memory cells Oct 30, 2007 Issued
Array ( [id] => 4758013 [patent_doc_number] => 20080310239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Device for writing data into memory and method thereof' [patent_app_type] => utility [patent_app_number] => 11/980506 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20080310239.pdf [firstpage_image] =>[orig_patent_app_number] => 11980506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980506
Device for writing data into memory and method thereof Oct 30, 2007 Issued
Array ( [id] => 4953767 [patent_doc_number] => 20080186791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Elastic Power for Read and Write Margins' [patent_app_type] => utility [patent_app_number] => 11/932967 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4884 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20080186791.pdf [firstpage_image] =>[orig_patent_app_number] => 11932967 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932967
Elastic power for read and write margins Oct 30, 2007 Issued
Array ( [id] => 4878248 [patent_doc_number] => 20080151631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Non-volatile memory device and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/980358 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6175 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151631.pdf [firstpage_image] =>[orig_patent_app_number] => 11980358 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980358
Non-volatile memory device and method of operating the same Oct 30, 2007 Issued
Array ( [id] => 5329269 [patent_doc_number] => 20090109746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'MEMORY CELL PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 11/932096 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12051 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109746.pdf [firstpage_image] =>[orig_patent_app_number] => 11932096 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/932096
Memory cell programming Oct 30, 2007 Issued
Array ( [id] => 114185 [patent_doc_number] => 07719896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-18 [patent_title] => 'Configurable single bit/dual bits memory' [patent_app_type] => utility [patent_app_number] => 11/981056 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3767 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719896.pdf [firstpage_image] =>[orig_patent_app_number] => 11981056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981056
Configurable single bit/dual bits memory Oct 29, 2007 Issued
Array ( [id] => 257362 [patent_doc_number] => 07577042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/978578 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577042.pdf [firstpage_image] =>[orig_patent_app_number] => 11978578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/978578
Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device Oct 29, 2007 Issued
Array ( [id] => 4892039 [patent_doc_number] => 20080101136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Semiconductor memory device having write data through function' [patent_app_type] => utility [patent_app_number] => 11/976720 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7153 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20080101136.pdf [firstpage_image] =>[orig_patent_app_number] => 11976720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976720
Semiconductor memory device having write data through function Oct 25, 2007 Issued
Array ( [id] => 4892028 [patent_doc_number] => 20080101125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Biasing circuit for EEPROM memories with shared latches' [patent_app_type] => utility [patent_app_number] => 11/977876 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9255 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20080101125.pdf [firstpage_image] =>[orig_patent_app_number] => 11977876 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/977876
Biasing circuit for EEPROM memories with shared latches Oct 25, 2007 Issued
Array ( [id] => 4914328 [patent_doc_number] => 20080094928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Semiconductor memory having data line separation switch' [patent_app_type] => utility [patent_app_number] => 11/976266 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4300 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094928.pdf [firstpage_image] =>[orig_patent_app_number] => 11976266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976266
Semiconductor memory having data line separation switch Oct 22, 2007 Abandoned
Array ( [id] => 44968 [patent_doc_number] => 07782651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Semiconductor device including storage device and method for driving the same' [patent_app_type] => utility [patent_app_number] => 11/976202 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 15111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782651.pdf [firstpage_image] =>[orig_patent_app_number] => 11976202 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976202
Semiconductor device including storage device and method for driving the same Oct 21, 2007 Issued
Array ( [id] => 4913526 [patent_doc_number] => 20080094125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Semiconductor integrated circuit device and semiconductor device including plurality of semiconductor circuits' [patent_app_type] => utility [patent_app_number] => 11/975470 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094125.pdf [firstpage_image] =>[orig_patent_app_number] => 11975470 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/975470
Semiconductor integrated circuit device and semiconductor device including plurality of semiconductor circuits Oct 18, 2007 Issued
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