
Huan Hoang
Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2154, 2827, 2511, 2818 |
| Total Applications | 3260 |
| Issued Applications | 3044 |
| Pending Applications | 110 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 850401
[patent_doc_number] => 07382645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-03
[patent_title] => 'Two terminal memory array having reference cells'
[patent_app_type] => utility
[patent_app_number] => 11/809643
[patent_app_country] => US
[patent_app_date] => 2007-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6995
[patent_no_of_claims] => 15
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[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/382/07382645.pdf
[firstpage_image] =>[orig_patent_app_number] => 11809643
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/809643 | Two terminal memory array having reference cells | May 31, 2007 | Issued |
Array
(
[id] => 5229446
[patent_doc_number] => 20070291553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'DATA OUTPUT CIRCUITS FOR AN INTEGRATED CIRCUIT MEMORY DEVICE IN WHICH DATA IS OUTPUT RESPONSIVE TO SELECTIVE INVOCATION OF A PLURALITY OF CLOCK SIGNALS, AND METHODS OF OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/755165
[patent_app_country] => US
[patent_app_date] => 2007-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4490
[patent_no_of_claims] => 28
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0291/20070291553.pdf
[firstpage_image] =>[orig_patent_app_number] => 11755165
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/755165 | Data output circuits for an integrated circuit memory device in which data is output responsive to selective invocation of a plurality of clock signals, and methods of operating the same | May 29, 2007 | Issued |
Array
(
[id] => 135459
[patent_doc_number] => 07697354
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-13
[patent_title] => 'Integrated circuit memory device responsive to word line/bit line short-circuit'
[patent_app_type] => utility
[patent_app_number] => 11/755101
[patent_app_country] => US
[patent_app_date] => 2007-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4064
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/697/07697354.pdf
[firstpage_image] =>[orig_patent_app_number] => 11755101
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/755101 | Integrated circuit memory device responsive to word line/bit line short-circuit | May 29, 2007 | Issued |
Array
(
[id] => 4709609
[patent_doc_number] => 20080298135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-04
[patent_title] => 'METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING AN ARRAY STRUCTURE COMPRISING THE SAME DEVICES'
[patent_app_type] => utility
[patent_app_number] => 11/755059
[patent_app_country] => US
[patent_app_date] => 2007-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3530
[patent_no_of_claims] => 38
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[pdf_file] => publications/A1/0298/20080298135.pdf
[firstpage_image] =>[orig_patent_app_number] => 11755059
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/755059 | Metal oxide semiconductor device and method for operating an array structure comprising the same devices | May 29, 2007 | Issued |
Array
(
[id] => 244267
[patent_doc_number] => 07590006
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-15
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/754531
[patent_app_country] => US
[patent_app_date] => 2007-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[pdf_file] => patents/07/590/07590006.pdf
[firstpage_image] =>[orig_patent_app_number] => 11754531
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754531 | Semiconductor memory device | May 28, 2007 | Issued |
Array
(
[id] => 353613
[patent_doc_number] => 07492639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-17
[patent_title] => 'EEPROM memory having an improved resistance to the breakdown of transistors'
[patent_app_type] => utility
[patent_app_number] => 11/754707
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[patent_app_date] => 2007-05-29
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[pdf_file] => patents/07/492/07492639.pdf
[firstpage_image] =>[orig_patent_app_number] => 11754707
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754707 | EEPROM memory having an improved resistance to the breakdown of transistors | May 28, 2007 | Issued |
Array
(
[id] => 16065
[patent_doc_number] => 07808844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-05
[patent_title] => 'Methods and apparatus for improved memory access'
[patent_app_type] => utility
[patent_app_number] => 11/806012
[patent_app_country] => US
[patent_app_date] => 2007-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 14258
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[pdf_file] => patents/07/808/07808844.pdf
[firstpage_image] =>[orig_patent_app_number] => 11806012
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/806012 | Methods and apparatus for improved memory access | May 28, 2007 | Issued |
Array
(
[id] => 5061632
[patent_doc_number] => 20070223271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-27
[patent_title] => 'Semiconductor memory device and semiconductor device group'
[patent_app_type] => utility
[patent_app_number] => 11/802812
[patent_app_country] => US
[patent_app_date] => 2007-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 6981
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[pdf_file] => publications/A1/0223/20070223271.pdf
[firstpage_image] =>[orig_patent_app_number] => 11802812
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/802812 | Semiconductor memory device and semiconductor device group | May 24, 2007 | Issued |
Array
(
[id] => 4763087
[patent_doc_number] => 20080174297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => 'CIRCUIT AND METHOD OF TESTING A FAIL IN A MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/754028
[patent_app_country] => US
[patent_app_date] => 2007-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0174/20080174297.pdf
[firstpage_image] =>[orig_patent_app_number] => 11754028
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754028 | Circuit and method of testing a fail in a memory device | May 24, 2007 | Issued |
Array
(
[id] => 4738520
[patent_doc_number] => 20080232172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'FLASH MEMORY DEVICE AND METHOD OF CONTROLLING PROGRAM VOLTAGE'
[patent_app_type] => utility
[patent_app_number] => 11/754037
[patent_app_country] => US
[patent_app_date] => 2007-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0232/20080232172.pdf
[firstpage_image] =>[orig_patent_app_number] => 11754037
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754037 | Flash memory device and method of controlling program voltage | May 24, 2007 | Issued |
Array
(
[id] => 125542
[patent_doc_number] => 07706189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-27
[patent_title] => 'Non-volatile storage system with transitional voltage during programming'
[patent_app_type] => utility
[patent_app_number] => 11/753963
[patent_app_country] => US
[patent_app_date] => 2007-05-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/706/07706189.pdf
[firstpage_image] =>[orig_patent_app_number] => 11753963
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/753963 | Non-volatile storage system with transitional voltage during programming | May 24, 2007 | Issued |
Array
(
[id] => 315861
[patent_doc_number] => 07525839
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-28
[patent_title] => 'Semiconductor memory device capable of correcting a read level properly'
[patent_app_type] => utility
[patent_app_number] => 11/753143
[patent_app_country] => US
[patent_app_date] => 2007-05-24
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[pdf_file] => patents/07/525/07525839.pdf
[firstpage_image] =>[orig_patent_app_number] => 11753143
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/753143 | Semiconductor memory device capable of correcting a read level properly | May 23, 2007 | Issued |
Array
(
[id] => 4790750
[patent_doc_number] => 20080291723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'SOURCE BIASING OF NOR-TYPE FLASH ARRAY WITH DYNAMICALLY VARIABLE SOURCE RESISTANCE'
[patent_app_type] => utility
[patent_app_number] => 11/752711
[patent_app_country] => US
[patent_app_date] => 2007-05-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0291/20080291723.pdf
[firstpage_image] =>[orig_patent_app_number] => 11752711
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/752711 | SOURCE BIASING OF NOR-TYPE FLASH ARRAY WITH DYNAMICALLY VARIABLE SOURCE RESISTANCE | May 22, 2007 | Abandoned |
Array
(
[id] => 357098
[patent_doc_number] => 07489540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-10
[patent_title] => 'Bitcell with variable-conductance transfer gate and method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/752051
[patent_app_country] => US
[patent_app_date] => 2007-05-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/489/07489540.pdf
[firstpage_image] =>[orig_patent_app_number] => 11752051
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/752051 | Bitcell with variable-conductance transfer gate and method thereof | May 21, 2007 | Issued |
Array
(
[id] => 4790747
[patent_doc_number] => 20080291720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'SPIN TORQUE TRANSFER MRAM DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/752157
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[firstpage_image] =>[orig_patent_app_number] => 11752157
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/752157 | Spin torque transfer MRAM device | May 21, 2007 | Issued |
Array
(
[id] => 4790794
[patent_doc_number] => 20080291767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL'
[patent_app_type] => utility
[patent_app_number] => 11/751315
[patent_app_country] => US
[patent_app_date] => 2007-05-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0291/20080291767.pdf
[firstpage_image] =>[orig_patent_app_number] => 11751315
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/751315 | MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL | May 20, 2007 | Abandoned |
Array
(
[id] => 572285
[patent_doc_number] => 07471556
[patent_country] => US
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[patent_issue_date] => 2008-12-30
[patent_title] => 'Local bank write buffers for accelerating a phase-change memory'
[patent_app_type] => utility
[patent_app_number] => 11/748595
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/748595 | Local bank write buffers for accelerating a phase-change memory | May 14, 2007 | Issued |
Array
(
[id] => 338988
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[patent_title] => 'High voltage detecting circuit for semiconductor memory device and method of controlling the same'
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Array
(
[id] => 4838509
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[patent_title] => 'MRAM Cell with Multiple Storage Elements'
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[firstpage_image] =>[orig_patent_app_number] => 11745903
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/745903 | MRAM cell with multiple storage elements | May 7, 2007 | Issued |
Array
(
[id] => 5027330
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[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/745051 | Semiconductor memory device and test method thereof | May 6, 2007 | Issued |