Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 279022 [patent_doc_number] => 07558104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Power saving in memory arrays' [patent_app_type] => utility [patent_app_number] => 11/702200 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3891 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558104.pdf [firstpage_image] =>[orig_patent_app_number] => 11702200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/702200
Power saving in memory arrays Feb 4, 2007 Issued
Array ( [id] => 5099970 [patent_doc_number] => 20070183231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Method of operating a memory system' [patent_app_type] => utility [patent_app_number] => 11/701926 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20070183231.pdf [firstpage_image] =>[orig_patent_app_number] => 11701926 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701926
Method of operating a memory system Feb 1, 2007 Abandoned
Array ( [id] => 364810 [patent_doc_number] => 07483290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Nonvolatile memory utilizing hot-carrier effect with data reversal function' [patent_app_type] => utility [patent_app_number] => 11/701958 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 11846 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483290.pdf [firstpage_image] =>[orig_patent_app_number] => 11701958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701958
Nonvolatile memory utilizing hot-carrier effect with data reversal function Feb 1, 2007 Issued
Array ( [id] => 808438 [patent_doc_number] => 07420845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'High-endurance memory device' [patent_app_type] => utility [patent_app_number] => 11/701886 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1999 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420845.pdf [firstpage_image] =>[orig_patent_app_number] => 11701886 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701886
High-endurance memory device Feb 1, 2007 Issued
Array ( [id] => 5251852 [patent_doc_number] => 20070133308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein' [patent_app_type] => utility [patent_app_number] => 11/657473 [patent_app_country] => US [patent_app_date] => 2007-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 32066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133308.pdf [firstpage_image] =>[orig_patent_app_number] => 11657473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657473
Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein Jan 24, 2007 Issued
Array ( [id] => 4536020 [patent_doc_number] => RE041880 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => reissue [patent_app_number] => 11/657380 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10677 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/041/RE041880.pdf [firstpage_image] =>[orig_patent_app_number] => 11657380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657380
Semiconductor memory device Jan 23, 2007 Issued
Array ( [id] => 4763826 [patent_doc_number] => 20080175037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'METHOD AND APPARATUS FOR HIGH-EFFICIENCY OPERATION OF A DYNAMIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 11/625572 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3474 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175037.pdf [firstpage_image] =>[orig_patent_app_number] => 11625572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625572
Method and apparatus for high-efficiency operation of a dynamic random access memory Jan 21, 2007 Issued
Array ( [id] => 264743 [patent_doc_number] => 07570514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Method of operating multi-level cell and integrate circuit for using multi-level cell to store data' [patent_app_type] => utility [patent_app_number] => 11/625456 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4305 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570514.pdf [firstpage_image] =>[orig_patent_app_number] => 11625456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625456
Method of operating multi-level cell and integrate circuit for using multi-level cell to store data Jan 21, 2007 Issued
Array ( [id] => 887694 [patent_doc_number] => 07352611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/655057 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7795 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352611.pdf [firstpage_image] =>[orig_patent_app_number] => 11655057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655057
Semiconductor integrated circuit Jan 18, 2007 Issued
Array ( [id] => 5003688 [patent_doc_number] => 20070201255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Chalcogenide glass constant current device, and its method of fabrication and operation' [patent_app_type] => utility [patent_app_number] => 11/653883 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201255.pdf [firstpage_image] =>[orig_patent_app_number] => 11653883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/653883
Chalcogenide glass constant current device, and its method of fabrication and operation Jan 16, 2007 Issued
Array ( [id] => 4806852 [patent_doc_number] => 20080170430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'CMOS SRAM/ROM UNIFIED BIT CELL' [patent_app_type] => utility [patent_app_number] => 11/652726 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170430.pdf [firstpage_image] =>[orig_patent_app_number] => 11652726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652726
CMOS SRAM/ROM unified bit cell Jan 11, 2007 Issued
Array ( [id] => 4806864 [patent_doc_number] => 20080170442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'Column leakage compensation in a sensing circuit' [patent_app_type] => utility [patent_app_number] => 11/652828 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3820 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170442.pdf [firstpage_image] =>[orig_patent_app_number] => 11652828 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652828
Column leakage compensation in a sensing circuit Jan 11, 2007 Issued
Array ( [id] => 4806876 [patent_doc_number] => 20080170454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'Sense amplifier with stages to reduce capacitance mismatch in current mirror load' [patent_app_type] => utility [patent_app_number] => 11/652770 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5633 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170454.pdf [firstpage_image] =>[orig_patent_app_number] => 11652770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652770
Sense amplifier with stages to reduce capacitance mismatch in current mirror load Jan 11, 2007 Issued
Array ( [id] => 45027 [patent_doc_number] => 07782695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Compensated current offset in a sensing circuit' [patent_app_type] => utility [patent_app_number] => 11/652742 [patent_app_country] => US [patent_app_date] => 2007-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5368 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782695.pdf [firstpage_image] =>[orig_patent_app_number] => 11652742 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/652742
Compensated current offset in a sensing circuit Jan 11, 2007 Issued
Array ( [id] => 186761 [patent_doc_number] => 07649764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Memory with shared write bit line(s)' [patent_app_type] => utility [patent_app_number] => 11/619808 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649764.pdf [firstpage_image] =>[orig_patent_app_number] => 11619808 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619808
Memory with shared write bit line(s) Jan 3, 2007 Issued
Array ( [id] => 4969865 [patent_doc_number] => 20070109867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Use of Data Latches in Cache Operations of Non-Volatile Memories' [patent_app_type] => utility [patent_app_number] => 11/619513 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14687 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109867.pdf [firstpage_image] =>[orig_patent_app_number] => 11619513 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619513
Use of data latches in cache operations of non-volatile memories Jan 2, 2007 Issued
Array ( [id] => 233805 [patent_doc_number] => 07599238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Semiconductor memory device and driving method thereof' [patent_app_type] => utility [patent_app_number] => 11/647318 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3623 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/599/07599238.pdf [firstpage_image] =>[orig_patent_app_number] => 11647318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647318
Semiconductor memory device and driving method thereof Dec 28, 2006 Issued
Array ( [id] => 4931724 [patent_doc_number] => 20080002499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Semiconductor memory apparatus having plurality of sense amplifier arrays having different activation timing' [patent_app_type] => utility [patent_app_number] => 11/647358 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2692 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20080002499.pdf [firstpage_image] =>[orig_patent_app_number] => 11647358 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647358
Semiconductor memory apparatus having plurality of sense amplifier arrays having different activation timing Dec 28, 2006 Issued
Array ( [id] => 4749788 [patent_doc_number] => 20080157859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'UNIFIED VOLTAGE GENERATION METHOD WITH IMPROVED POWER EFFICIENCY' [patent_app_type] => utility [patent_app_number] => 11/618522 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157859.pdf [firstpage_image] =>[orig_patent_app_number] => 11618522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618522
Unified voltage generation method with improved power efficiency Dec 28, 2006 Issued
Array ( [id] => 357105 [patent_doc_number] => 07489547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Method of NAND flash memory cell array with adaptive memory state partitioning' [patent_app_type] => utility [patent_app_number] => 11/618482 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 9552 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489547.pdf [firstpage_image] =>[orig_patent_app_number] => 11618482 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618482
Method of NAND flash memory cell array with adaptive memory state partitioning Dec 28, 2006 Issued
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