Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 338968 [patent_doc_number] => 07505313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Program method of flash memory capable of compensating reduction of read margin between states due to hot temperature stress' [patent_app_type] => utility [patent_app_number] => 11/593478 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5236 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/505/07505313.pdf [firstpage_image] =>[orig_patent_app_number] => 11593478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593478
Program method of flash memory capable of compensating reduction of read margin between states due to hot temperature stress Nov 6, 2006 Issued
Array ( [id] => 135456 [patent_doc_number] => 07697351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Circuit and method for controlling internal voltage of semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 11/593032 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2592 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/697/07697351.pdf [firstpage_image] =>[orig_patent_app_number] => 11593032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593032
Circuit and method for controlling internal voltage of semiconductor memory apparatus Nov 5, 2006 Issued
Array ( [id] => 4964140 [patent_doc_number] => 20080106960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Memory device architecture and method for improved bitline pre-charge and wordline timing' [patent_app_type] => utility [patent_app_number] => 11/593444 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4367 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20080106960.pdf [firstpage_image] =>[orig_patent_app_number] => 11593444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593444
Memory device architecture and method for improved bitline pre-charge and wordline timing Nov 5, 2006 Issued
Array ( [id] => 5214934 [patent_doc_number] => 20070104014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency' [patent_app_type] => utility [patent_app_number] => 11/593234 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5167 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20070104014.pdf [firstpage_image] =>[orig_patent_app_number] => 11593234 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593234
Circuit arrangement for generating an n-bit output pointer, semiconductor memory and method for adjusting a read latency Nov 5, 2006 Issued
Array ( [id] => 594752 [patent_doc_number] => 07443762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Synchronization circuit for a write operation on a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/593236 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6786 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443762.pdf [firstpage_image] =>[orig_patent_app_number] => 11593236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593236
Synchronization circuit for a write operation on a semiconductor memory Nov 5, 2006 Issued
Array ( [id] => 4823161 [patent_doc_number] => 20080123416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Program and erase methods and structures for byte-alterable flash memory' [patent_app_type] => utility [patent_app_number] => 11/593398 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4756 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20080123416.pdf [firstpage_image] =>[orig_patent_app_number] => 11593398 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593398
Program and erase methods and structures for byte-alterable flash memory Nov 5, 2006 Issued
Array ( [id] => 5251846 [patent_doc_number] => 20070133302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Electrically writable non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/592162 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5200 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133302.pdf [firstpage_image] =>[orig_patent_app_number] => 11592162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/592162
Electrically writable non-volatile memory Nov 2, 2006 Issued
Array ( [id] => 804724 [patent_doc_number] => 07423924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/589708 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5211 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/423/07423924.pdf [firstpage_image] =>[orig_patent_app_number] => 11589708 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589708
Semiconductor memory device Oct 30, 2006 Issued
Array ( [id] => 187076 [patent_doc_number] => 07646624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Method of selecting operating characteristics of a resistive memory device' [patent_app_type] => utility [patent_app_number] => 11/590378 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 3890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646624.pdf [firstpage_image] =>[orig_patent_app_number] => 11590378 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590378
Method of selecting operating characteristics of a resistive memory device Oct 30, 2006 Issued
Array ( [id] => 4942967 [patent_doc_number] => 20080080292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Control component for controlling a semiconductor memory component in a semiconductor memory module' [patent_app_type] => utility [patent_app_number] => 11/589984 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6648 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080292.pdf [firstpage_image] =>[orig_patent_app_number] => 11589984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589984
Control component for controlling a semiconductor memory component in a semiconductor memory module Oct 30, 2006 Issued
Array ( [id] => 895112 [patent_doc_number] => 07345924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Programming memory devices' [patent_app_type] => utility [patent_app_number] => 11/546171 [patent_app_country] => US [patent_app_date] => 2006-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/345/07345924.pdf [firstpage_image] =>[orig_patent_app_number] => 11546171 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546171
Programming memory devices Oct 10, 2006 Issued
Array ( [id] => 4692003 [patent_doc_number] => 20080084774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'FLOATING BODY CONTROL IN SOI DRAM' [patent_app_type] => utility [patent_app_number] => 11/534070 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2755 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20080084774.pdf [firstpage_image] =>[orig_patent_app_number] => 11534070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/534070
Floating body control in SOI DRAM Sep 20, 2006 Issued
Array ( [id] => 4823202 [patent_doc_number] => 20080123446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Randomizing Current Consumption in Memory Devices' [patent_app_type] => utility [patent_app_number] => 11/533908 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6620 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20080123446.pdf [firstpage_image] =>[orig_patent_app_number] => 11533908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533908
Randomizing current consumption in memory devices Sep 20, 2006 Issued
Array ( [id] => 5134870 [patent_doc_number] => 20070076499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Semiconductor storage device and electronic equipment' [patent_app_type] => utility [patent_app_number] => 11/516642 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18716 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20070076499.pdf [firstpage_image] =>[orig_patent_app_number] => 11516642 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516642
Semiconductor storage device and electronic equipment Sep 6, 2006 Issued
Array ( [id] => 912754 [patent_doc_number] => 07330392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-12 [patent_title] => 'Dual port semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/470826 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6704 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330392.pdf [firstpage_image] =>[orig_patent_app_number] => 11470826 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470826
Dual port semiconductor memory device Sep 6, 2006 Issued
Array ( [id] => 5203666 [patent_doc_number] => 20070025145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'NON-VOLATILE MEMORY CELL USING HIGH-K MATERIAL AND INTER-GATE PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 11/470932 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13240 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20070025145.pdf [firstpage_image] =>[orig_patent_app_number] => 11470932 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470932
Non-volatile memory cell using high-K material and inter-gate programming Sep 6, 2006 Issued
Array ( [id] => 594326 [patent_doc_number] => 07443712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Memory erase management system' [patent_app_type] => utility [patent_app_number] => 11/470958 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443712.pdf [firstpage_image] =>[orig_patent_app_number] => 11470958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470958
Memory erase management system Sep 6, 2006 Issued
Array ( [id] => 244257 [patent_doc_number] => 07589995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'One-transistor memory cell with bias gate' [patent_app_type] => utility [patent_app_number] => 11/516814 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 36 [patent_no_of_words] => 5267 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589995.pdf [firstpage_image] =>[orig_patent_app_number] => 11516814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516814
One-transistor memory cell with bias gate Sep 6, 2006 Issued
Array ( [id] => 4770337 [patent_doc_number] => 20080055995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Programming non-volatile memory with improved boosting' [patent_app_type] => utility [patent_app_number] => 11/516976 [patent_app_country] => US [patent_app_date] => 2006-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14561 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20080055995.pdf [firstpage_image] =>[orig_patent_app_number] => 11516976 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516976
Programming non-volatile memory with improved boosting Sep 5, 2006 Issued
Array ( [id] => 596508 [patent_doc_number] => 07440308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Phase-change random access memory device and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/515422 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7867 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440308.pdf [firstpage_image] =>[orig_patent_app_number] => 11515422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515422
Phase-change random access memory device and method of operating the same Sep 4, 2006 Issued
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