Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5055489 [patent_doc_number] => 20070058410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Methods and apparatus of stacking DRAMs' [patent_app_type] => utility [patent_app_number] => 11/515406 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14340 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20070058410.pdf [firstpage_image] =>[orig_patent_app_number] => 11515406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/515406
Methods and apparatus of stacking DRAMs Aug 31, 2006 Issued
Array ( [id] => 380704 [patent_doc_number] => 07310281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-18 [patent_title] => 'Semiconductor memories with refreshing cycles' [patent_app_type] => utility [patent_app_number] => 11/514648 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2019 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310281.pdf [firstpage_image] =>[orig_patent_app_number] => 11514648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514648
Semiconductor memories with refreshing cycles Aug 31, 2006 Issued
Array ( [id] => 370762 [patent_doc_number] => 07477537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/504079 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 10205 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/477/07477537.pdf [firstpage_image] =>[orig_patent_app_number] => 11504079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504079
Semiconductor integrated circuit device Aug 14, 2006 Issued
Array ( [id] => 5886284 [patent_doc_number] => 20060274571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/504077 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10178 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20060274571.pdf [firstpage_image] =>[orig_patent_app_number] => 11504077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504077
Semiconductor integrated circuit device Aug 14, 2006 Issued
Array ( [id] => 430099 [patent_doc_number] => 07269089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Divisible true dual port memory system supporting simple dual port memory subsystems' [patent_app_type] => utility [patent_app_number] => 11/501616 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269089.pdf [firstpage_image] =>[orig_patent_app_number] => 11501616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501616
Divisible true dual port memory system supporting simple dual port memory subsystems Aug 7, 2006 Issued
Array ( [id] => 5607102 [patent_doc_number] => 20060268618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Non-Volatile System with Program Time Control' [patent_app_type] => utility [patent_app_number] => 11/462920 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3917 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20060268618.pdf [firstpage_image] =>[orig_patent_app_number] => 11462920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462920
Non-volatile system with program time control Aug 6, 2006 Issued
Array ( [id] => 422676 [patent_doc_number] => 07274611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Method and architecture to calibrate read operations in synchronous flash memory' [patent_app_type] => utility [patent_app_number] => 11/495404 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3749 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274611.pdf [firstpage_image] =>[orig_patent_app_number] => 11495404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495404
Method and architecture to calibrate read operations in synchronous flash memory Jul 27, 2006 Issued
Array ( [id] => 5624104 [patent_doc_number] => 20060262609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Non-volatile semiconductor memory device and semiconductor disk device' [patent_app_type] => utility [patent_app_number] => 11/492929 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9341 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20060262609.pdf [firstpage_image] =>[orig_patent_app_number] => 11492929 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492929
Non-volatile semiconductor memory device and semiconductor disk device Jul 25, 2006 Issued
Array ( [id] => 7531513 [patent_doc_number] => 07843742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Method of controlling memory and memory system thereof' [patent_app_type] => utility [patent_app_number] => 11/996544 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/843/07843742.pdf [firstpage_image] =>[orig_patent_app_number] => 11996544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/996544
Method of controlling memory and memory system thereof Jul 25, 2006 Issued
Array ( [id] => 5660248 [patent_doc_number] => 20060250844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Systems-On-Chips Including Programmed Memory Cells and Programmable and Erasable Memory Cells' [patent_app_type] => utility [patent_app_number] => 11/459547 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3522 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250844.pdf [firstpage_image] =>[orig_patent_app_number] => 11459547 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/459547
Systems-on-chips including programmed memory cells and programmable and erasable memory cells Jul 23, 2006 Issued
Array ( [id] => 4908421 [patent_doc_number] => 20080019187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Memory device and method for verifying information stored in memory cells' [patent_app_type] => utility [patent_app_number] => 11/489702 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5241 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20080019187.pdf [firstpage_image] =>[orig_patent_app_number] => 11489702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/489702
Memory device and method for verifying information stored in memory cells Jul 18, 2006 Issued
Array ( [id] => 5544405 [patent_doc_number] => 20090154282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/094770 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7908 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20090154282.pdf [firstpage_image] =>[orig_patent_app_number] => 12094770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/094770
Semiconductor device Jul 5, 2006 Issued
Array ( [id] => 5833433 [patent_doc_number] => 20060245263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/477649 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 28854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245263.pdf [firstpage_image] =>[orig_patent_app_number] => 11477649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477649
Nonvolatile semiconductor memory Jun 29, 2006 Issued
Array ( [id] => 478596 [patent_doc_number] => 07227775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Two terminal memory array having reference cells' [patent_app_type] => utility [patent_app_number] => 11/478520 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6995 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227775.pdf [firstpage_image] =>[orig_patent_app_number] => 11478520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478520
Two terminal memory array having reference cells Jun 28, 2006 Issued
Array ( [id] => 482278 [patent_doc_number] => 07224603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-29 [patent_title] => 'SRAM cell controlled by flash memory cell' [patent_app_type] => utility [patent_app_number] => 11/427456 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2993 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224603.pdf [firstpage_image] =>[orig_patent_app_number] => 11427456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/427456
SRAM cell controlled by flash memory cell Jun 28, 2006 Issued
Array ( [id] => 827758 [patent_doc_number] => 07403421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Noise reduction technique for transistors and small devices utilizing an episodic agitation' [patent_app_type] => utility [patent_app_number] => 11/426082 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 14315 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/403/07403421.pdf [firstpage_image] =>[orig_patent_app_number] => 11426082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426082
Noise reduction technique for transistors and small devices utilizing an episodic agitation Jun 22, 2006 Issued
Array ( [id] => 5229454 [patent_doc_number] => 20070291561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'SENSE-AMPLIFIER ASSIST (SAA) WITH POWER-REDUCTION TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 11/424072 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4501 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20070291561.pdf [firstpage_image] =>[orig_patent_app_number] => 11424072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424072
SENSE-AMPLIFIER ASSIST (SAA) WITH POWER-REDUCTION TECHNIQUE Jun 13, 2006 Abandoned
Array ( [id] => 5229435 [patent_doc_number] => 20070291542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Programming method for NAND flash' [patent_app_type] => utility [patent_app_number] => 11/452698 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8084 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20070291542.pdf [firstpage_image] =>[orig_patent_app_number] => 11452698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/452698
Programming method for NAND flash Jun 13, 2006 Issued
Array ( [id] => 282843 [patent_doc_number] => 07554845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'EEPROM cell and EEPROM block' [patent_app_type] => utility [patent_app_number] => 11/451442 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3770 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554845.pdf [firstpage_image] =>[orig_patent_app_number] => 11451442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451442
EEPROM cell and EEPROM block Jun 12, 2006 Issued
Array ( [id] => 5833450 [patent_doc_number] => 20060245280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Integrated circuit having a non-volatile memory cell transistor as a fuse device' [patent_app_type] => utility [patent_app_number] => 11/451441 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5494 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245280.pdf [firstpage_image] =>[orig_patent_app_number] => 11451441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451441
Integrated circuit having a non-volatile memory cell transistor as a fuse device Jun 12, 2006 Issued
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