
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 282843
[patent_doc_number] => 07554845
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[patent_issue_date] => 2009-06-30
[patent_title] => 'EEPROM cell and EEPROM block'
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[pdf_file] => patents/07/554/07554845.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451442 | EEPROM cell and EEPROM block | Jun 12, 2006 | Issued |
Array
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[patent_doc_number] => 20060245280
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[patent_issue_date] => 2006-11-02
[patent_title] => 'Integrated circuit having a non-volatile memory cell transistor as a fuse device'
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Array
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[patent_doc_number] => 20070230264
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[patent_issue_date] => 2007-10-04
[patent_title] => 'Dynamic semiconductor memory reducing the frequency of occurrence of refresh command request and refresh control method thereof'
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Array
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[patent_title] => 'Non-volatile memory and method with bit line to bit line coupled compensation'
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Array
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[patent_title] => 'CONTROL SIGNAL INTERFACE CIRCUIT FOR COMPUTER MEMORY MODULES'
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Array
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[patent_title] => 'Method and apparatus for programming flash memory'
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Array
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Array
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[patent_title] => 'Non-volatile memory and control with improved partial page program capability'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/381972 | Non-volatile memory and control with improved partial page program capability | May 4, 2006 | Issued |
Array
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[patent_title] => 'Non-Volatile Memory with Background Data Latch Caching During Erase Operations'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/381998 | Non-volatile memory with background data latch caching during erase operations | May 4, 2006 | Issued |
Array
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[patent_title] => 'Method for Non-Volatile Memory with Background Data Latch Caching During Erase Operations'
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[patent_app_number] => 11/382001
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Array
(
[id] => 490081
[patent_doc_number] => 07218551
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[patent_title] => 'Multiple level cell memory device with single bit per cell, re-mappable memory block'
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Array
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[patent_title] => 'Bitline leakage limiting with improved voltage regulation'
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Array
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Array
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