Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 282843 [patent_doc_number] => 07554845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'EEPROM cell and EEPROM block' [patent_app_type] => utility [patent_app_number] => 11/451442 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3770 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554845.pdf [firstpage_image] =>[orig_patent_app_number] => 11451442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451442
EEPROM cell and EEPROM block Jun 12, 2006 Issued
Array ( [id] => 5833450 [patent_doc_number] => 20060245280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Integrated circuit having a non-volatile memory cell transistor as a fuse device' [patent_app_type] => utility [patent_app_number] => 11/451441 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5494 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245280.pdf [firstpage_image] =>[orig_patent_app_number] => 11451441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451441
Integrated circuit having a non-volatile memory cell transistor as a fuse device Jun 12, 2006 Issued
Array ( [id] => 5090625 [patent_doc_number] => 20070230264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Dynamic semiconductor memory reducing the frequency of occurrence of refresh command request and refresh control method thereof' [patent_app_type] => utility [patent_app_number] => 11/450472 [patent_app_country] => US [patent_app_date] => 2006-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10237 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20070230264.pdf [firstpage_image] =>[orig_patent_app_number] => 11450472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450472
Dynamic semiconductor memory reducing the frequency of occurrence of refresh command request and refresh control method thereof Jun 11, 2006 Issued
Array ( [id] => 430032 [patent_doc_number] => 07269069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Non-volatile memory and method with bit line to bit line coupled compensation' [patent_app_type] => utility [patent_app_number] => 11/422034 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 10986 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269069.pdf [firstpage_image] =>[orig_patent_app_number] => 11422034 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422034
Non-volatile memory and method with bit line to bit line coupled compensation Jun 1, 2006 Issued
Array ( [id] => 5641549 [patent_doc_number] => 20060280004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'CONTROL SIGNAL INTERFACE CIRCUIT FOR COMPUTER MEMORY MODULES' [patent_app_type] => utility [patent_app_number] => 11/420454 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2244 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20060280004.pdf [firstpage_image] =>[orig_patent_app_number] => 11420454 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420454
Control signal interface circuit for computer memory modules May 24, 2006 Issued
Array ( [id] => 5044777 [patent_doc_number] => 20070263449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method and apparatus for programming flash memory' [patent_app_type] => utility [patent_app_number] => 11/433562 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4792 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263449.pdf [firstpage_image] =>[orig_patent_app_number] => 11433562 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433562
Method and apparatus for programming flash memory May 14, 2006 Issued
Array ( [id] => 5752533 [patent_doc_number] => 20060221682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same' [patent_app_type] => utility [patent_app_number] => 11/433653 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3956 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20060221682.pdf [firstpage_image] =>[orig_patent_app_number] => 11433653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433653
Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same May 11, 2006 Issued
Array ( [id] => 416647 [patent_doc_number] => 07280396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Non-volatile memory and control with improved partial page program capability' [patent_app_type] => utility [patent_app_number] => 11/381972 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 14701 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/280/07280396.pdf [firstpage_image] =>[orig_patent_app_number] => 11381972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381972
Non-volatile memory and control with improved partial page program capability May 4, 2006 Issued
Array ( [id] => 5849830 [patent_doc_number] => 20060233021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Non-Volatile Memory with Background Data Latch Caching During Erase Operations' [patent_app_type] => utility [patent_app_number] => 11/381998 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 30431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20060233021.pdf [firstpage_image] =>[orig_patent_app_number] => 11381998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381998
Non-volatile memory with background data latch caching during erase operations May 4, 2006 Issued
Array ( [id] => 5849832 [patent_doc_number] => 20060233023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Method for Non-Volatile Memory with Background Data Latch Caching During Erase Operations' [patent_app_type] => utility [patent_app_number] => 11/382001 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 30420 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20060233023.pdf [firstpage_image] =>[orig_patent_app_number] => 11382001 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/382001
Method for non-volatile memory with background data latch caching during erase operations May 4, 2006 Issued
Array ( [id] => 490081 [patent_doc_number] => 07218551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Multiple level cell memory device with single bit per cell, re-mappable memory block' [patent_app_type] => utility [patent_app_number] => 11/417572 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218551.pdf [firstpage_image] =>[orig_patent_app_number] => 11417572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/417572
Multiple level cell memory device with single bit per cell, re-mappable memory block May 3, 2006 Issued
Array ( [id] => 5223999 [patent_doc_number] => 20070253265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Bitline leakage limiting with improved voltage regulation' [patent_app_type] => utility [patent_app_number] => 11/414364 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4178 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253265.pdf [firstpage_image] =>[orig_patent_app_number] => 11414364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414364
Bitline leakage limiting with improved voltage regulation Apr 30, 2006 Issued
Array ( [id] => 923994 [patent_doc_number] => 07319613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'NROM flash memory cell with integrated DRAM' [patent_app_type] => utility [patent_app_number] => 11/415384 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3590 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/319/07319613.pdf [firstpage_image] =>[orig_patent_app_number] => 11415384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/415384
NROM flash memory cell with integrated DRAM Apr 30, 2006 Issued
Array ( [id] => 409864 [patent_doc_number] => 07286377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh' [patent_app_type] => utility [patent_app_number] => 11/412960 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 19884 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286377.pdf [firstpage_image] =>[orig_patent_app_number] => 11412960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/412960
Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh Apr 27, 2006 Issued
Array ( [id] => 419665 [patent_doc_number] => 07277325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/412938 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 7552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/277/07277325.pdf [firstpage_image] =>[orig_patent_app_number] => 11412938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/412938
Semiconductor memory device Apr 27, 2006 Issued
Array ( [id] => 5607140 [patent_doc_number] => 20060268656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'External clock synchronization semiconductor memory device and method for controlling same' [patent_app_type] => utility [patent_app_number] => 11/413008 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6096 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20060268656.pdf [firstpage_image] =>[orig_patent_app_number] => 11413008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413008
External clock synchronization semiconductor memory device and method for controlling same Apr 27, 2006 Issued
Array ( [id] => 430009 [patent_doc_number] => 07269056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Power grid design for split-word line style memory cell' [patent_app_type] => utility [patent_app_number] => 11/412752 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4514 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269056.pdf [firstpage_image] =>[orig_patent_app_number] => 11412752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/412752
Power grid design for split-word line style memory cell Apr 26, 2006 Issued
Array ( [id] => 5618179 [patent_doc_number] => 20060187712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Reduction of adjacent floating gate data pattern sensitivity' [patent_app_type] => utility [patent_app_number] => 11/403738 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20060187712.pdf [firstpage_image] =>[orig_patent_app_number] => 11403738 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/403738
Reduction of adjacent floating gate data pattern sensitivity Apr 12, 2006 Issued
Array ( [id] => 5618183 [patent_doc_number] => 20060187716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Reduction of adjacent floating gate data pattern sensitivity' [patent_app_type] => utility [patent_app_number] => 11/403780 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3652 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20060187716.pdf [firstpage_image] =>[orig_patent_app_number] => 11403780 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/403780
Reduction of adjacent floating gate data pattern sensitivity Apr 12, 2006 Issued
Array ( [id] => 5681923 [patent_doc_number] => 20060198193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Reduction of adjacent floating gate data pattern sensitivity' [patent_app_type] => utility [patent_app_number] => 11/403781 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20060198193.pdf [firstpage_image] =>[orig_patent_app_number] => 11403781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/403781
Reduction of adjacent floating gate data pattern sensitivity Apr 12, 2006 Issued
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