Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 557314 [patent_doc_number] => 07170811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-30 [patent_title] => 'Separate variable power supply to on-chip memory using existing power supplies' [patent_app_type] => utility [patent_app_number] => 11/216388 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2622 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170811.pdf [firstpage_image] =>[orig_patent_app_number] => 11216388 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216388
Separate variable power supply to on-chip memory using existing power supplies Aug 30, 2005 Issued
Array ( [id] => 6930073 [patent_doc_number] => 20050281107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/209753 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5548 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20050281107.pdf [firstpage_image] =>[orig_patent_app_number] => 11209753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209753
Semiconductor memory with sense amplifier equalizer having transistors with gate oxide films of different thicknesses Aug 23, 2005 Issued
Array ( [id] => 5714388 [patent_doc_number] => 20060077751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Latency control circuit and method of latency control' [patent_app_type] => utility [patent_app_number] => 11/202314 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 14080 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20060077751.pdf [firstpage_image] =>[orig_patent_app_number] => 11202314 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202314
Latency control circuit and method of latency control Aug 11, 2005 Issued
Array ( [id] => 862627 [patent_doc_number] => 07372765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Power-gating system and method for integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 11/198031 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4284 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372765.pdf [firstpage_image] =>[orig_patent_app_number] => 11198031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/198031
Power-gating system and method for integrated circuit devices Aug 4, 2005 Issued
Array ( [id] => 7220621 [patent_doc_number] => 20050254337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Latency control circuit and method of latency control' [patent_app_type] => utility [patent_app_number] => 11/188708 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9232 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20050254337.pdf [firstpage_image] =>[orig_patent_app_number] => 11188708 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188708
Latency control circuit and method of latency control Jul 25, 2005 Issued
Array ( [id] => 7220438 [patent_doc_number] => 20050254295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Sensing scheme for programmable resistance memory using voltage coefficient characteristics' [patent_app_type] => utility [patent_app_number] => 11/183917 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3662 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20050254295.pdf [firstpage_image] =>[orig_patent_app_number] => 11183917 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183917
Sensing scheme for programmable resistance memory using voltage coefficient characteristics Jul 18, 2005 Issued
Array ( [id] => 589078 [patent_doc_number] => 07453727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Nonvolatile semiconductor memory and method for setting replacement information in nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/179680 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 11722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/453/07453727.pdf [firstpage_image] =>[orig_patent_app_number] => 11179680 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/179680
Nonvolatile semiconductor memory and method for setting replacement information in nonvolatile semiconductor memory Jul 12, 2005 Issued
Array ( [id] => 5140393 [patent_doc_number] => 20070002609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'MRAM embedded smart power integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/170874 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20070002609.pdf [firstpage_image] =>[orig_patent_app_number] => 11170874 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170874
MRAM embedded smart power integrated circuits Jun 29, 2005 Issued
Array ( [id] => 5782374 [patent_doc_number] => 20060203588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/168924 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10931 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203588.pdf [firstpage_image] =>[orig_patent_app_number] => 11168924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/168924
Semiconductor memory Jun 28, 2005 Issued
Array ( [id] => 413282 [patent_doc_number] => 07283382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Minimization of signal loss due to self-erase of imprinted data' [patent_app_type] => utility [patent_app_number] => 11/171663 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3912 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/283/07283382.pdf [firstpage_image] =>[orig_patent_app_number] => 11171663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171663
Minimization of signal loss due to self-erase of imprinted data Jun 28, 2005 Issued
Array ( [id] => 763753 [patent_doc_number] => 07012851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Nonvolatile ferroelectric memory device with split word lines' [patent_app_type] => utility [patent_app_number] => 11/167854 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 14760 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012851.pdf [firstpage_image] =>[orig_patent_app_number] => 11167854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/167854
Nonvolatile ferroelectric memory device with split word lines Jun 27, 2005 Issued
Array ( [id] => 463477 [patent_doc_number] => 07242615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/167303 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6307 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242615.pdf [firstpage_image] =>[orig_patent_app_number] => 11167303 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/167303
Non-volatile semiconductor memory device Jun 27, 2005 Issued
Array ( [id] => 7602647 [patent_doc_number] => 07236388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Driving method of variable resistance element and memory device' [patent_app_type] => utility [patent_app_number] => 11/169535 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14932 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236388.pdf [firstpage_image] =>[orig_patent_app_number] => 11169535 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169535
Driving method of variable resistance element and memory device Jun 27, 2005 Issued
Array ( [id] => 6965101 [patent_doc_number] => 20050231998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Nonvolatile ferroelectric memory device with split word lines' [patent_app_type] => utility [patent_app_number] => 11/167159 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14732 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20050231998.pdf [firstpage_image] =>[orig_patent_app_number] => 11167159 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/167159
Nonvolatile ferroelectric memory device with split word lines Jun 27, 2005 Issued
Array ( [id] => 874832 [patent_doc_number] => 07362626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Asynchronous, high-bandwidth memory component using calibrated timing elements' [patent_app_type] => utility [patent_app_number] => 11/165797 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 38 [patent_no_of_words] => 19276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362626.pdf [firstpage_image] =>[orig_patent_app_number] => 11165797 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/165797
Asynchronous, high-bandwidth memory component using calibrated timing elements Jun 23, 2005 Issued
Array ( [id] => 697625 [patent_doc_number] => 07072213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'NROM flash memory cell with integrated DRAM' [patent_app_type] => utility [patent_app_number] => 11/159692 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3649 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/072/07072213.pdf [firstpage_image] =>[orig_patent_app_number] => 11159692 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159692
NROM flash memory cell with integrated DRAM Jun 22, 2005 Issued
Array ( [id] => 409886 [patent_doc_number] => 07286388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Resistive memory device with improved data retention' [patent_app_type] => utility [patent_app_number] => 11/165005 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4454 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286388.pdf [firstpage_image] =>[orig_patent_app_number] => 11165005 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/165005
Resistive memory device with improved data retention Jun 22, 2005 Issued
Array ( [id] => 531676 [patent_doc_number] => 07187599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Integrated circuit chip having a first delay circuit trimmed via a second delay circuit' [patent_app_type] => utility [patent_app_number] => 11/137736 [patent_app_country] => US [patent_app_date] => 2005-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7604 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187599.pdf [firstpage_image] =>[orig_patent_app_number] => 11137736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/137736
Integrated circuit chip having a first delay circuit trimmed via a second delay circuit May 24, 2005 Issued
Array ( [id] => 7017910 [patent_doc_number] => 20050219928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Offset compensated sensing for magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 11/133236 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4353 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20050219928.pdf [firstpage_image] =>[orig_patent_app_number] => 11133236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/133236
Offset compensated sensing for magnetic random access memory May 19, 2005 Issued
Array ( [id] => 499104 [patent_doc_number] => 07212457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Method and apparatus for implementing high speed memory' [patent_app_type] => utility [patent_app_number] => 11/131580 [patent_app_country] => US [patent_app_date] => 2005-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3179 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212457.pdf [firstpage_image] =>[orig_patent_app_number] => 11131580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131580
Method and apparatus for implementing high speed memory May 17, 2005 Issued
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