Search

Huan Hoang

Examiner (ID: 2059)

Most Active Art Unit
2827
Art Unit(s)
2511, 2827, 2818, 2154
Total Applications
3262
Issued Applications
3045
Pending Applications
111
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7017910 [patent_doc_number] => 20050219928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Offset compensated sensing for magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 11/133236 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4353 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20050219928.pdf [firstpage_image] =>[orig_patent_app_number] => 11133236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/133236
Offset compensated sensing for magnetic random access memory May 19, 2005 Issued
Array ( [id] => 499104 [patent_doc_number] => 07212457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Method and apparatus for implementing high speed memory' [patent_app_type] => utility [patent_app_number] => 11/131580 [patent_app_country] => US [patent_app_date] => 2005-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3179 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212457.pdf [firstpage_image] =>[orig_patent_app_number] => 11131580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131580
Method and apparatus for implementing high speed memory May 17, 2005 Issued
Array ( [id] => 5746793 [patent_doc_number] => 20060109724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Memory device capable of changing data output mode' [patent_app_type] => utility [patent_app_number] => 11/131544 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7264 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109724.pdf [firstpage_image] =>[orig_patent_app_number] => 11131544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131544
Memory device capable of changing data output mode May 16, 2005 Issued
Array ( [id] => 430097 [patent_doc_number] => 07269088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Identical chips with different operations in a system' [patent_app_type] => utility [patent_app_number] => 11/131572 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4397 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269088.pdf [firstpage_image] =>[orig_patent_app_number] => 11131572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131572
Identical chips with different operations in a system May 16, 2005 Issued
Array ( [id] => 455590 [patent_doc_number] => 07248517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Semiconductor memory device having local data line pair with delayed precharge voltage application point' [patent_app_type] => utility [patent_app_number] => 11/128878 [patent_app_country] => US [patent_app_date] => 2005-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3373 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248517.pdf [firstpage_image] =>[orig_patent_app_number] => 11128878 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128878
Semiconductor memory device having local data line pair with delayed precharge voltage application point May 13, 2005 Issued
Array ( [id] => 528134 [patent_doc_number] => 07190626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Memory system with bit-line discharging mechanism' [patent_app_type] => utility [patent_app_number] => 11/128846 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2562 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190626.pdf [firstpage_image] =>[orig_patent_app_number] => 11128846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128846
Memory system with bit-line discharging mechanism May 12, 2005 Issued
Array ( [id] => 924006 [patent_doc_number] => 07319617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Small sector floating gate flash memory' [patent_app_type] => utility [patent_app_number] => 11/129646 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 10025 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/319/07319617.pdf [firstpage_image] =>[orig_patent_app_number] => 11129646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/129646
Small sector floating gate flash memory May 12, 2005 Issued
Array ( [id] => 644133 [patent_doc_number] => 07123524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Input circuit having updated output signal synchronized to clock signal' [patent_app_type] => utility [patent_app_number] => 11/128688 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 15056 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123524.pdf [firstpage_image] =>[orig_patent_app_number] => 11128688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128688
Input circuit having updated output signal synchronized to clock signal May 12, 2005 Issued
Array ( [id] => 5812186 [patent_doc_number] => 20060083060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Flexible OTP sector protection architecture for flash memories' [patent_app_type] => utility [patent_app_number] => 11/128648 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3312 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083060.pdf [firstpage_image] =>[orig_patent_app_number] => 11128648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/128648
Flexible OTP sector protection architecture for flash memories May 11, 2005 Issued
Array ( [id] => 652205 [patent_doc_number] => 07113421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/127286 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 10169 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113421.pdf [firstpage_image] =>[orig_patent_app_number] => 11127286 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127286
Semiconductor integrated circuit device May 11, 2005 Issued
Array ( [id] => 478634 [patent_doc_number] => 07227789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method and apparatus for filtering output data' [patent_app_type] => utility [patent_app_number] => 11/127526 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3786 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227789.pdf [firstpage_image] =>[orig_patent_app_number] => 11127526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127526
Method and apparatus for filtering output data May 11, 2005 Issued
Array ( [id] => 512086 [patent_doc_number] => 07203092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Flash memory array using adjacent bit line as source' [patent_app_type] => utility [patent_app_number] => 11/127466 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4167 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203092.pdf [firstpage_image] =>[orig_patent_app_number] => 11127466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127466
Flash memory array using adjacent bit line as source May 11, 2005 Issued
Array ( [id] => 487008 [patent_doc_number] => 07221617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Backwards-compatible memory module' [patent_app_type] => utility [patent_app_number] => 11/127536 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6809 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221617.pdf [firstpage_image] =>[orig_patent_app_number] => 11127536 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127536
Backwards-compatible memory module May 11, 2005 Issued
Array ( [id] => 5731489 [patent_doc_number] => 20060256603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Dual-edged DIMM to support memory expansion' [patent_app_type] => utility [patent_app_number] => 11/127516 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2909 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20060256603.pdf [firstpage_image] =>[orig_patent_app_number] => 11127516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127516
Dual-edged DIMM to support memory expansion May 11, 2005 Issued
Array ( [id] => 7220513 [patent_doc_number] => 20050254316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Semiconductor device and control method of the same' [patent_app_type] => utility [patent_app_number] => 11/127712 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11379 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20050254316.pdf [firstpage_image] =>[orig_patent_app_number] => 11127712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127712
Semiconductor device and control method of the same May 11, 2005 Issued
Array ( [id] => 531580 [patent_doc_number] => 07187589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/127022 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187589.pdf [firstpage_image] =>[orig_patent_app_number] => 11127022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127022
Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory May 10, 2005 Issued
Array ( [id] => 430029 [patent_doc_number] => 07269066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Programming memory devices' [patent_app_type] => utility [patent_app_number] => 11/126790 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3984 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269066.pdf [firstpage_image] =>[orig_patent_app_number] => 11126790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126790
Programming memory devices May 10, 2005 Issued
Array ( [id] => 5731494 [patent_doc_number] => 20060256608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Resistive memory device with improved data retention and reduced power' [patent_app_type] => utility [patent_app_number] => 11/126800 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3684 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20060256608.pdf [firstpage_image] =>[orig_patent_app_number] => 11126800 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126800
Resistive memory device with improved data retention and reduced power May 10, 2005 Abandoned
Array ( [id] => 7005271 [patent_doc_number] => 20050170584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Compact and highly efficient DRAM cell' [patent_app_type] => utility [patent_app_number] => 11/092288 [patent_app_country] => US [patent_app_date] => 2005-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2516 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170584.pdf [firstpage_image] =>[orig_patent_app_number] => 11092288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/092288
Compact and highly efficient DRAM cell Mar 28, 2005 Issued
Array ( [id] => 7189190 [patent_doc_number] => 20050162968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Semiconductor integrated device' [patent_app_type] => utility [patent_app_number] => 11/087827 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8552 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162968.pdf [firstpage_image] =>[orig_patent_app_number] => 11087827 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/087827
Semiconductor integrated device Mar 23, 2005 Issued
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