Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 463516 [patent_doc_number] => 07242633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Memory device and method of transferring data in memory device' [patent_app_type] => utility [patent_app_number] => 11/044740 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7121 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242633.pdf [firstpage_image] =>[orig_patent_app_number] => 11044740 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044740
Memory device and method of transferring data in memory device Jan 25, 2005 Issued
Array ( [id] => 455515 [patent_doc_number] => 07248491 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-24 [patent_title] => 'Circuit for and method of implementing a content addressable memory in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/044746 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7140 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248491.pdf [firstpage_image] =>[orig_patent_app_number] => 11044746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044746
Circuit for and method of implementing a content addressable memory in a programmable logic device Jan 25, 2005 Issued
Array ( [id] => 5871354 [patent_doc_number] => 20060164887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'METHOD AND APPARATUS FOR CHANGING OPERATING CONDITIONS OF NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/043550 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3145 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20060164887.pdf [firstpage_image] =>[orig_patent_app_number] => 11043550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/043550
Method and apparatus for changing operating conditions of nonvolatile memory Jan 25, 2005 Issued
Array ( [id] => 647722 [patent_doc_number] => 07120058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Circuit and method for controlling boosting voltage' [patent_app_type] => utility [patent_app_number] => 11/042608 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3590 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120058.pdf [firstpage_image] =>[orig_patent_app_number] => 11042608 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042608
Circuit and method for controlling boosting voltage Jan 24, 2005 Issued
Array ( [id] => 5871351 [patent_doc_number] => 20060164884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method of dynamically controlling program verify levels in multilevel memory cells' [patent_app_type] => utility [patent_app_number] => 11/043854 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9149 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20060164884.pdf [firstpage_image] =>[orig_patent_app_number] => 11043854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/043854
Method of dynamically controlling program verify levels in multilevel memory cells Jan 24, 2005 Issued
Array ( [id] => 636020 [patent_doc_number] => 07130238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-31 [patent_title] => 'Divisible true dual port memory system supporting simple dual port memory subsystems' [patent_app_type] => utility [patent_app_number] => 11/041120 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130238.pdf [firstpage_image] =>[orig_patent_app_number] => 11041120 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041120
Divisible true dual port memory system supporting simple dual port memory subsystems Jan 20, 2005 Issued
Array ( [id] => 498833 [patent_doc_number] => 07212422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Stacked layered type semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/038526 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212422.pdf [firstpage_image] =>[orig_patent_app_number] => 11038526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038526
Stacked layered type semiconductor memory device Jan 20, 2005 Issued
Array ( [id] => 498833 [patent_doc_number] => 07212422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Stacked layered type semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/038526 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212422.pdf [firstpage_image] =>[orig_patent_app_number] => 11038526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038526
Stacked layered type semiconductor memory device Jan 20, 2005 Issued
Array ( [id] => 7189110 [patent_doc_number] => 20050162950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Stacked layered type semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/038532 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7787 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162950.pdf [firstpage_image] =>[orig_patent_app_number] => 11038532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038532
Stacked layered type semiconductor memory device Jan 20, 2005 Issued
Array ( [id] => 7245573 [patent_doc_number] => 20050141309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage' [patent_app_type] => utility [patent_app_number] => 11/040959 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6205 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141309.pdf [firstpage_image] =>[orig_patent_app_number] => 11040959 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040959
Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage Jan 18, 2005 Issued
Array ( [id] => 732623 [patent_doc_number] => 07042747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-09 [patent_title] => 'Ternary CAM bitcells' [patent_app_type] => utility [patent_app_number] => 11/041094 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042747.pdf [firstpage_image] =>[orig_patent_app_number] => 11041094 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041094
Ternary CAM bitcells Jan 18, 2005 Issued
Array ( [id] => 7188964 [patent_doc_number] => 20050162925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Non-volatile memory cell array having common drain lines and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/038726 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162925.pdf [firstpage_image] =>[orig_patent_app_number] => 11038726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038726
Non-volatile memory cell array having common drain lines and method of operating the same Jan 18, 2005 Issued
Array ( [id] => 528085 [patent_doc_number] => 07190622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Method and architecture to calibrate read operations in synchronous flash memory' [patent_app_type] => utility [patent_app_number] => 11/036402 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3753 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190622.pdf [firstpage_image] =>[orig_patent_app_number] => 11036402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036402
Method and architecture to calibrate read operations in synchronous flash memory Jan 13, 2005 Issued
Array ( [id] => 6994002 [patent_doc_number] => 20050133778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Chalcogenide glass constant current device, and its method of fabrication and operation' [patent_app_type] => utility [patent_app_number] => 11/033873 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9230 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133778.pdf [firstpage_image] =>[orig_patent_app_number] => 11033873 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033873
Methods of operating and forming chalcogenide glass constant current devices Jan 12, 2005 Issued
Array ( [id] => 377931 [patent_doc_number] => 07313035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Methods and apparatus for improved memory access' [patent_app_type] => utility [patent_app_number] => 11/030881 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14217 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313035.pdf [firstpage_image] =>[orig_patent_app_number] => 11030881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030881
Methods and apparatus for improved memory access Jan 9, 2005 Issued
90/007360 INTEGRATED MEMORY HAVING CELLS AND REFERENCE CELLS, AND OPERATING METHOD FOR SUCH A MEMORY Jan 2, 2005 Pending
Array ( [id] => 912706 [patent_doc_number] => 07330370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-12 [patent_title] => 'Enhanced functionality in a two-terminal memory array' [patent_app_type] => utility [patent_app_number] => 11/021600 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6456 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330370.pdf [firstpage_image] =>[orig_patent_app_number] => 11021600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021600
Enhanced functionality in a two-terminal memory array Dec 22, 2004 Issued
Array ( [id] => 942218 [patent_doc_number] => 06970378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-29 [patent_title] => 'Thin-film magnetic memory device executing data writing with data write magnetic fields in two directions' [patent_app_type] => utility [patent_app_number] => 11/003504 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 18148 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/970/06970378.pdf [firstpage_image] =>[orig_patent_app_number] => 11003504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003504
Thin-film magnetic memory device executing data writing with data write magnetic fields in two directions Dec 5, 2004 Issued
Array ( [id] => 5763242 [patent_doc_number] => 20060017181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Semiconductor memory device and semiconductor device group' [patent_app_type] => utility [patent_app_number] => 10/988530 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6964 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20060017181.pdf [firstpage_image] =>[orig_patent_app_number] => 10988530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988530
Semiconductor memory device and semiconductor device group Nov 15, 2004 Issued
Array ( [id] => 7073698 [patent_doc_number] => 20050146965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Semiconductor memory device having internal circuits responsive to temperature data and method thereof' [patent_app_type] => utility [patent_app_number] => 10/981652 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7457 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146965.pdf [firstpage_image] =>[orig_patent_app_number] => 10981652 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981652
Semiconductor memory device having internal circuits responsive to temperature data and method thereof Nov 4, 2004 Issued
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