Search

Huan Hoang

Examiner (ID: 8099, Phone: (571)272-1779 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2154, 2827, 2511, 2818
Total Applications
3260
Issued Applications
3044
Pending Applications
110
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6943608 [patent_doc_number] => 20050195657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Bit switch voltage drop compensation during programming in nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 10/792120 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6236 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195657.pdf [firstpage_image] =>[orig_patent_app_number] => 10792120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/792120
Bit switch voltage drop compensation during programming in nonvolatile memory Mar 2, 2004 Issued
Array ( [id] => 7245446 [patent_doc_number] => 20050141287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Power-up circuit in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/792064 [patent_app_country] => US [patent_app_date] => 2004-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4777 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20050141287.pdf [firstpage_image] =>[orig_patent_app_number] => 10792064 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/792064
Power-up circuit in semiconductor memory device Mar 1, 2004 Issued
Array ( [id] => 701780 [patent_doc_number] => 07068547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Internal voltage generating circuit in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/792065 [patent_app_country] => US [patent_app_date] => 2004-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2219 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068547.pdf [firstpage_image] =>[orig_patent_app_number] => 10792065 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/792065
Internal voltage generating circuit in semiconductor memory device Mar 1, 2004 Issued
Array ( [id] => 7380187 [patent_doc_number] => 20040179421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Semiconductor memory device capable of generating variable clock signals according to modes of operation' [patent_app_type] => new [patent_app_number] => 10/790262 [patent_app_country] => US [patent_app_date] => 2004-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8457 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20040179421.pdf [firstpage_image] =>[orig_patent_app_number] => 10790262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/790262
Semiconductor memory device capable of generating variable clock signals according to modes of operation Feb 29, 2004 Issued
Array ( [id] => 1108154 [patent_doc_number] => 06813185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Non-volatile semiconductor memory device and semiconductor disk device' [patent_app_type] => B2 [patent_app_number] => 10/786007 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9288 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813185.pdf [firstpage_image] =>[orig_patent_app_number] => 10786007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786007
Non-volatile semiconductor memory device and semiconductor disk device Feb 25, 2004 Issued
Array ( [id] => 7380151 [patent_doc_number] => 20040179416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Memory device, refresh control circuit to be used for the memory device, and refresh method' [patent_app_type] => new [patent_app_number] => 10/786834 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8941 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20040179416.pdf [firstpage_image] =>[orig_patent_app_number] => 10786834 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786834
Memory device, refresh control circuit to be used for the memory device, and refresh method Feb 24, 2004 Issued
Array ( [id] => 697630 [patent_doc_number] => 07072215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm' [patent_app_type] => utility [patent_app_number] => 10/785522 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3955 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/072/07072215.pdf [firstpage_image] =>[orig_patent_app_number] => 10785522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785522
Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm Feb 23, 2004 Issued
Array ( [id] => 977304 [patent_doc_number] => 06934191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/783019 [patent_app_country] => US [patent_app_date] => 2004-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 7322 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934191.pdf [firstpage_image] =>[orig_patent_app_number] => 10783019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/783019
Nonvolatile semiconductor memory device Feb 22, 2004 Issued
Array ( [id] => 939196 [patent_doc_number] => 06972986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown' [patent_app_type] => utility [patent_app_number] => 10/782564 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5490 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972986.pdf [firstpage_image] =>[orig_patent_app_number] => 10782564 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782564
Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown Feb 17, 2004 Issued
Array ( [id] => 7134695 [patent_doc_number] => 20050180224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Differential current-mode sensing methods and apparatuses for memories' [patent_app_type] => utility [patent_app_number] => 10/779464 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10877 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20050180224.pdf [firstpage_image] =>[orig_patent_app_number] => 10779464 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779464
Differential current-mode sensing methods and apparatuses for memories Feb 12, 2004 Issued
Array ( [id] => 682523 [patent_doc_number] => 07085180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and structure for enabling a redundancy allocation during a multi-bank operation' [patent_app_type] => utility [patent_app_number] => 10/777596 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4058 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085180.pdf [firstpage_image] =>[orig_patent_app_number] => 10777596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777596
Method and structure for enabling a redundancy allocation during a multi-bank operation Feb 11, 2004 Issued
Array ( [id] => 682521 [patent_doc_number] => 07085179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Integrated circuit having a non-volatile memory cell transistor as a fuse device' [patent_app_type] => utility [patent_app_number] => 10/776600 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5460 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085179.pdf [firstpage_image] =>[orig_patent_app_number] => 10776600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776600
Integrated circuit having a non-volatile memory cell transistor as a fuse device Feb 11, 2004 Issued
Array ( [id] => 7204492 [patent_doc_number] => 20050052931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)' [patent_app_type] => utility [patent_app_number] => 10/776103 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4327 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052931.pdf [firstpage_image] =>[orig_patent_app_number] => 10776103 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776103
Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM) Feb 10, 2004 Issued
Array ( [id] => 879314 [patent_doc_number] => 07359277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation' [patent_app_type] => utility [patent_app_number] => 10/776101 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2928 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359277.pdf [firstpage_image] =>[orig_patent_app_number] => 10776101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776101
High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation Feb 10, 2004 Issued
Array ( [id] => 6911089 [patent_doc_number] => 20050174847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'NROM FLASH MEMORY CELL WITH INTEGRATED DRAM' [patent_app_type] => utility [patent_app_number] => 10/775424 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3604 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174847.pdf [firstpage_image] =>[orig_patent_app_number] => 10775424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/775424
NROM flash memory cell with integrated DRAM Feb 9, 2004 Issued
Array ( [id] => 7421151 [patent_doc_number] => 20040160826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Memory with row redundancy' [patent_app_type] => new [patent_app_number] => 10/774868 [patent_app_country] => US [patent_app_date] => 2004-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5022 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160826.pdf [firstpage_image] =>[orig_patent_app_number] => 10774868 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/774868
Memory with row redundancy Feb 8, 2004 Issued
Array ( [id] => 7315775 [patent_doc_number] => 20040223354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Semiconductor memory device having high-speed input/output architecture' [patent_app_type] => new [patent_app_number] => 10/773464 [patent_app_country] => US [patent_app_date] => 2004-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2684 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20040223354.pdf [firstpage_image] =>[orig_patent_app_number] => 10773464 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/773464
Semiconductor memory device having high-speed input/output architecture Feb 8, 2004 Issued
Array ( [id] => 7614391 [patent_doc_number] => 06898139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation' [patent_app_type] => utility [patent_app_number] => 10/773024 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9301 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898139.pdf [firstpage_image] =>[orig_patent_app_number] => 10773024 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/773024
Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation Feb 4, 2004 Issued
Array ( [id] => 980435 [patent_doc_number] => 06930935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Redundancy circuit and semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 10/770422 [patent_app_country] => US [patent_app_date] => 2004-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 19167 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930935.pdf [firstpage_image] =>[orig_patent_app_number] => 10770422 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770422
Redundancy circuit and semiconductor device using the same Feb 3, 2004 Issued
Array ( [id] => 7257251 [patent_doc_number] => 20040240289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Semiconductor integrated device' [patent_app_type] => new [patent_app_number] => 10/769818 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8700 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240289.pdf [firstpage_image] =>[orig_patent_app_number] => 10769818 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769818
Semiconductor integrated device Feb 2, 2004 Issued
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