
Huan Hoang
Examiner (ID: 2059)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2511, 2827, 2818, 2154 |
| Total Applications | 3262 |
| Issued Applications | 3045 |
| Pending Applications | 111 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1003744
[patent_doc_number] => 06909660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-21
[patent_title] => 'Random access memory having driver for reduced leakage current'
[patent_app_type] => utility
[patent_app_number] => 10/672118
[patent_app_country] => US
[patent_app_date] => 2003-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2953
[patent_no_of_claims] => 28
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[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/909/06909660.pdf
[firstpage_image] =>[orig_patent_app_number] => 10672118
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672118 | Random access memory having driver for reduced leakage current | Sep 25, 2003 | Issued |
Array
(
[id] => 7611850
[patent_doc_number] => 06903989
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'Data sensing circuits and methods for magnetic memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/668022
[patent_app_country] => US
[patent_app_date] => 2003-09-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/903/06903989.pdf
[firstpage_image] =>[orig_patent_app_number] => 10668022
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668022 | Data sensing circuits and methods for magnetic memory devices | Sep 21, 2003 | Issued |
Array
(
[id] => 7126221
[patent_doc_number] => 20050057965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-17
[patent_title] => 'NON-VOLATILE MEMORY AND METHOD WITH BIT LINE COUPLED COMPENSATION'
[patent_app_type] => utility
[patent_app_number] => 10/667222
[patent_app_country] => US
[patent_app_date] => 2003-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[pdf_file] => publications/A1/0057/20050057965.pdf
[firstpage_image] =>[orig_patent_app_number] => 10667222
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/667222 | Non-volatile memory and method with bit line coupled compensation | Sep 16, 2003 | Issued |
Array
(
[id] => 954522
[patent_doc_number] => 06958939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-25
[patent_title] => 'Flash memory cell having multi-program channels'
[patent_app_type] => utility
[patent_app_number] => 10/663425
[patent_app_country] => US
[patent_app_date] => 2003-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2414
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[pdf_file] => patents/06/958/06958939.pdf
[firstpage_image] =>[orig_patent_app_number] => 10663425
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/663425 | Flash memory cell having multi-program channels | Sep 14, 2003 | Issued |
Array
(
[id] => 1003748
[patent_doc_number] => 06909662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-21
[patent_title] => 'Data read circuit in a semiconductor device featuring reduced chip area and increased data transfer rate'
[patent_app_type] => utility
[patent_app_number] => 10/660518
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/909/06909662.pdf
[firstpage_image] =>[orig_patent_app_number] => 10660518
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/660518 | Data read circuit in a semiconductor device featuring reduced chip area and increased data transfer rate | Sep 11, 2003 | Issued |
Array
(
[id] => 7454455
[patent_doc_number] => 20040052128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'High speed memory array architecture'
[patent_app_type] => new
[patent_app_number] => 10/660566
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0052/20040052128.pdf
[firstpage_image] =>[orig_patent_app_number] => 10660566
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/660566 | System and method for operating a memory array | Sep 11, 2003 | Issued |
Array
(
[id] => 1007135
[patent_doc_number] => 06906946
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'Compact and highly efficient DRAM cell'
[patent_app_type] => utility
[patent_app_number] => 10/657848
[patent_app_country] => US
[patent_app_date] => 2003-09-09
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[pdf_file] => patents/06/906/06906946.pdf
[firstpage_image] =>[orig_patent_app_number] => 10657848
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657848 | Compact and highly efficient DRAM cell | Sep 8, 2003 | Issued |
Array
(
[id] => 7606503
[patent_doc_number] => 07099216
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-29
[patent_title] => 'Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing'
[patent_app_type] => utility
[patent_app_number] => 10/656596
[patent_app_country] => US
[patent_app_date] => 2003-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/07/099/07099216.pdf
[firstpage_image] =>[orig_patent_app_number] => 10656596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/656596 | Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing | Sep 4, 2003 | Issued |
Array
(
[id] => 7131936
[patent_doc_number] => 20040042328
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Magnetic material, memory and information reproducing method of the same'
[patent_app_type] => new
[patent_app_number] => 10/651935
[patent_app_country] => US
[patent_app_date] => 2003-09-02
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[pdf_file] => publications/A1/0042/20040042328.pdf
[firstpage_image] =>[orig_patent_app_number] => 10651935
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/651935 | Magnetic material, memory and information reproducing method of the same | Sep 1, 2003 | Abandoned |
Array
(
[id] => 7162971
[patent_doc_number] => 20040076058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Integrated DRAM memory component'
[patent_app_type] => new
[patent_app_number] => 10/650818
[patent_app_country] => US
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[pdf_file] => publications/A1/0076/20040076058.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650818
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650818 | Integrated DRAM memory component | Aug 27, 2003 | Issued |
Array
(
[id] => 7131913
[patent_doc_number] => 20040042314
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[patent_title] => 'Semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/652920 | Semiconductor memory device | Aug 27, 2003 | Issued |
Array
(
[id] => 7398376
[patent_doc_number] => 20040174760
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[patent_title] => 'Integrated circuit memory device including delay locked loop circuit and delay locked loop control circuit and method of controlling delay locked loop circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/646718 | Integrated circuit memory device including delay locked loop circuit and delay locked loop control circuit and method of controlling delay locked loop circuit | Aug 24, 2003 | Issued |
Array
(
[id] => 7191287
[patent_doc_number] => 20050040455
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[patent_title] => 'Non-volatile multi-stable memory device and methods of making and using the same'
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Array
(
[id] => 1067388
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[patent_title] => 'Method for operating NOR type flash memory device including SONOS cells'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/643724 | Method for operating NOR type flash memory device including SONOS cells | Aug 17, 2003 | Issued |
Array
(
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[patent_title] => 'Nonvolatile semiconductor memory device, nonvolatile semiconductor memory device-integrated system, and defective block detecting method'
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Array
(
[id] => 1099320
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[patent_title] => 'SRAM-compatible memory device employing DRAM cells'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639922 | SRAM-compatible memory device employing DRAM cells | Aug 11, 2003 | Issued |
Array
(
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[patent_title] => 'Non-volatile semiconductor memory device and data write control method for the same'
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/625122 | Semiconductor memory device having advanced prefetch block | Jul 21, 2003 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/522316 | Composite storage circuit and semiconductor device having the same composite storage circuit | Jul 21, 2003 | Issued |