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Huedung Xuan Cao Mancuso

Examiner (ID: 153, Phone: (571)272-1939 , Office: P/2845 )

Most Active Art Unit
2821
Art Unit(s)
2772, 2671, 2821, 2845
Total Applications
1508
Issued Applications
1276
Pending Applications
51
Abandoned Applications
190

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19892028 [patent_doc_number] => 20250117340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/985285 [patent_app_country] => US [patent_app_date] => 2024-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 95403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18985285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/985285
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM Dec 17, 2024 Pending
Array ( [id] => 19893047 [patent_doc_number] => 20250118359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => DUMMY DATA-BASED READ REFERENCE VOLTAGE SEARCH OF NAND MEMORY [patent_app_type] => utility [patent_app_number] => 18/984515 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984515 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984515
DUMMY DATA-BASED READ REFERENCE VOLTAGE SEARCH OF NAND MEMORY Dec 16, 2024 Pending
Array ( [id] => 19892330 [patent_doc_number] => 20250117642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/983284 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18983284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/983284
METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK Dec 15, 2024 Pending
Array ( [id] => 19865969 [patent_doc_number] => 20250104755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/973584 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18973584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/973584
SEMICONDUCTOR DEVICE Dec 8, 2024 Pending
Array ( [id] => 20063060 [patent_doc_number] => 20250201282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => AUTOMATIC SINGLE-USE-DEVICE VOLTAGE COMPATIBILITY [patent_app_type] => utility [patent_app_number] => 18/972688 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18972688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/972688
AUTOMATIC SINGLE-USE-DEVICE VOLTAGE COMPATIBILITY Dec 5, 2024 Pending
Array ( [id] => 19850395 [patent_doc_number] => 20250095746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 18/967011 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967011
DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT Dec 2, 2024 Pending
Array ( [id] => 20036034 [patent_doc_number] => 20250174256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => CONFIGURATION MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/962961 [patent_app_country] => US [patent_app_date] => 2024-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18962961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/962961
CONFIGURATION MEMORY CELL Nov 26, 2024 Pending
Array ( [id] => 20520165 [patent_doc_number] => 20260044271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/960150 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960150
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM Nov 25, 2024 Pending
Array ( [id] => 20739459 [patent_doc_number] => 20260148765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => MEMORY CIRCUITS AND METHODS FOR LATCHING READOUT IN MULTI-BANK SRAM MEMORY [patent_app_type] => utility [patent_app_number] => 18/960648 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960648
MEMORY CIRCUITS AND METHODS FOR LATCHING READOUT IN MULTI-BANK SRAM MEMORY Nov 25, 2024 Pending
Array ( [id] => 20741271 [patent_doc_number] => 20260150589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => PHASE CHANGE MEMORY CELL HAVING A HEATER WITH ACTIVATED RESISTANCE IN TEMPERATURE, AND IN-MEMORY COMPUTATION CIRCUIT USING SUCH A PHASE CHANGE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/958125 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958125
PHASE CHANGE MEMORY CELL HAVING A HEATER WITH ACTIVATED RESISTANCE IN TEMPERATURE, AND IN-MEMORY COMPUTATION CIRCUIT USING SUCH A PHASE CHANGE MEMORY CELL Nov 24, 2024 Pending
Array ( [id] => 20044616 [patent_doc_number] => 20250182838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/954613 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954613
STORAGE DEVICE Nov 20, 2024 Pending
Array ( [id] => 20381521 [patent_doc_number] => 20250364014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/954739 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954739
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME Nov 20, 2024 Pending
Array ( [id] => 19820714 [patent_doc_number] => 20250078921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DUO-LEVEL WORD LINE DRIVER [patent_app_type] => utility [patent_app_number] => 18/954783 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954783
DUO-LEVEL WORD LINE DRIVER Nov 20, 2024 Pending
Array ( [id] => 19835506 [patent_doc_number] => 20250087292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON [patent_app_type] => utility [patent_app_number] => 18/953302 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18953302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/953302
BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON Nov 19, 2024 Pending
Array ( [id] => 19820721 [patent_doc_number] => 20250078928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY DEVICE, OPERATING METHOD THEREOF, SYSTEM, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/954002 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954002
MEMORY DEVICE, OPERATING METHOD THEREOF, SYSTEM, AND STORAGE MEDIUM Nov 19, 2024 Pending
Array ( [id] => 19820712 [patent_doc_number] => 20250078919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => METHOD OF OPERATING AN INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/948746 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948746 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948746
METHOD OF OPERATING AN INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT Nov 14, 2024 Pending
Array ( [id] => 19820677 [patent_doc_number] => 20250078884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => BUFFER CONFIGURATIONS FOR COMMUNICATIONS BETWEEN MEMORY DIES AND A HOST DEVICE [patent_app_type] => utility [patent_app_number] => 18/948310 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948310
BUFFER CONFIGURATIONS FOR COMMUNICATIONS BETWEEN MEMORY DIES AND A HOST DEVICE Nov 13, 2024 Pending
Array ( [id] => 19803747 [patent_doc_number] => 20250069672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => COLUMN CONTROL CIRCUITS AND STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/948283 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948283
COLUMN CONTROL CIRCUITS AND STORAGE DEVICES Nov 13, 2024 Pending
Array ( [id] => 20821920 [patent_doc_number] => 12677408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-07 [patent_title] => Memory device using semiconductor element [patent_app_type] => utility [patent_app_number] => 18/942990 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 4994 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18942990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/942990
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT Nov 10, 2024 Issued
Array ( [id] => 20124263 [patent_doc_number] => 20250239294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/937180 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/937180
MEMORY DEVICE AND METHOD OF OPERATING THE SAME Nov 4, 2024 Pending
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