Search

Huedung Xuan Cao Mancuso

Examiner (ID: 153, Phone: (571)272-1939 , Office: P/2845 )

Most Active Art Unit
2821
Art Unit(s)
2772, 2671, 2821, 2845
Total Applications
1508
Issued Applications
1276
Pending Applications
51
Abandoned Applications
190

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18900580 [patent_doc_number] => 20240016065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => MAGNETORESISTIVE MEMORY DEVICE INCLUDING A MAGNETORESISTANCE AMPLIFICATION LAYER [patent_app_type] => utility [patent_app_number] => 17/810710 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810710
Magnetoresistive memory device including a magnetoresistance amplification layer Jul 4, 2022 Issued
Array ( [id] => 18607846 [patent_doc_number] => 11749322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Copy data in a memory system with artificial intelligence mode [patent_app_type] => utility [patent_app_number] => 17/856099 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8195 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856099
Copy data in a memory system with artificial intelligence mode Jun 30, 2022 Issued
Array ( [id] => 17948997 [patent_doc_number] => 20220336016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => RRAM CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 17/856811 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856811
RRAM circuit and method Jun 30, 2022 Issued
Array ( [id] => 19414532 [patent_doc_number] => 12080366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Method of error correction code (ECC) decoding and memory system performing the same [patent_app_type] => utility [patent_app_number] => 17/854638 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 16400 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854638
Method of error correction code (ECC) decoding and memory system performing the same Jun 29, 2022 Issued
Array ( [id] => 18455851 [patent_doc_number] => 20230197132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => Doping Process To Refine Grain Size For Smoother BiSb Film Surface [patent_app_type] => utility [patent_app_number] => 17/854568 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854568
Doping process to refine grain size for smoother BiSb film surface Jun 29, 2022 Issued
Array ( [id] => 19294324 [patent_doc_number] => 12033685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Method for adjusting margin, circuit for adjusting margin and memory [patent_app_type] => utility [patent_app_number] => 17/854273 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854273
Method for adjusting margin, circuit for adjusting margin and memory Jun 29, 2022 Issued
Array ( [id] => 19213469 [patent_doc_number] => 12002541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Read clock toggle at configurable PAM levels [patent_app_type] => utility [patent_app_number] => 17/854924 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854924
Read clock toggle at configurable PAM levels Jun 29, 2022 Issued
Array ( [id] => 18472889 [patent_doc_number] => 20230207177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SYNTHETIC ANTIFERROMAGNET, MAGNETIC TUNNELING JUNCTION DEVICE INCLUDING THE SYNTHETIC ANTIFERROMAGNET, AND MEMORY DEVICE INCLUDING THE MAGNETIC TUNNELING JUNCTION DEVICE [patent_app_type] => utility [patent_app_number] => 17/847099 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17847099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/847099
Synthetic antiferromagnet, magnetic tunneling junction device including the synthetic antiferromagnet, and memory device including the magnetic tunneling junction device Jun 21, 2022 Issued
Array ( [id] => 19093696 [patent_doc_number] => 11955160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Asynchronous signal to command timing calibration for testing accuracy [patent_app_type] => utility [patent_app_number] => 17/846967 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846967
Asynchronous signal to command timing calibration for testing accuracy Jun 21, 2022 Issued
Array ( [id] => 18848492 [patent_doc_number] => 20230410896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Multi-Port Memory Architecture [patent_app_type] => utility [patent_app_number] => 17/844551 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844551
Multi-port memory architecture Jun 19, 2022 Issued
Array ( [id] => 18528511 [patent_doc_number] => 11715509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/836213 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 45 [patent_no_of_words] => 23270 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836213
Semiconductor device Jun 8, 2022 Issued
Array ( [id] => 18528534 [patent_doc_number] => 11715532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-01 [patent_title] => Risk assessment method based on data priority, memory storage device, and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 17/833901 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7071 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833901 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833901
Risk assessment method based on data priority, memory storage device, and memory control circuit unit Jun 6, 2022 Issued
Array ( [id] => 17870452 [patent_doc_number] => 20220293189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => WEAK ERASE PULSE [patent_app_type] => utility [patent_app_number] => 17/829837 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829837
Weak erase pulse May 31, 2022 Issued
Array ( [id] => 17854914 [patent_doc_number] => 20220284957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => MULTI-STEP PRE-READ FOR WRITE OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/824776 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824776
Multi-step pre-read for write operations in memory devices May 24, 2022 Issued
Array ( [id] => 19137816 [patent_doc_number] => 11972787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Cross-point array refresh scheme [patent_app_type] => utility [patent_app_number] => 17/824806 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 26647 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824806
Cross-point array refresh scheme May 24, 2022 Issued
Array ( [id] => 17870444 [patent_doc_number] => 20220293181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => TRACKING OPERATIONS PERFORMED AT A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/751453 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751453
Tracking operations performed at a memory device May 22, 2022 Issued
Array ( [id] => 18787862 [patent_doc_number] => 20230376229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => FAST AND FLEXIBLE RAM READER AND WRITER [patent_app_type] => utility [patent_app_number] => 17/663847 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663847
Fast and flexible RAM reader and writer May 17, 2022 Issued
Array ( [id] => 19108466 [patent_doc_number] => 11961579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Bit line noise suppression and related apparatuses, methods, and computing systems [patent_app_type] => utility [patent_app_number] => 17/663888 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663888
Bit line noise suppression and related apparatuses, methods, and computing systems May 17, 2022 Issued
Array ( [id] => 19153603 [patent_doc_number] => 11978525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Base die, memory system, and semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/662064 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662064
Base die, memory system, and semiconductor structure May 3, 2022 Issued
Array ( [id] => 18507370 [patent_doc_number] => 11705194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Systems and techniques for accessing multiple memory cells concurrently [patent_app_type] => utility [patent_app_number] => 17/733683 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733683
Systems and techniques for accessing multiple memory cells concurrently Apr 28, 2022 Issued
Menu