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Huedung Xuan Cao Mancuso

Examiner (ID: 153, Phone: (571)272-1939 , Office: P/2845 )

Most Active Art Unit
2821
Art Unit(s)
2772, 2671, 2821, 2845
Total Applications
1508
Issued Applications
1276
Pending Applications
51
Abandoned Applications
190

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16904516 [patent_doc_number] => 20210183432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/161403 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161403
Memory device comprising electrically floating body transistor Jan 27, 2021 Issued
Array ( [id] => 17683223 [patent_doc_number] => 11367484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-21 [patent_title] => Multi-step pre-read for write operations in memory devices [patent_app_type] => utility [patent_app_number] => 17/154644 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154644
Multi-step pre-read for write operations in memory devices Jan 20, 2021 Issued
Array ( [id] => 16811791 [patent_doc_number] => 20210134346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/150514 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150514 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150514
Redundant voltage regulator for memory devices Jan 14, 2021 Issued
Array ( [id] => 17737752 [patent_doc_number] => 20220223214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY APPARATUS AND METHOD OF OPERATION USING PLANE DEPENDENT RAMP RATE AND TIMING CONTROL FOR PROGRAM OPERATION [patent_app_type] => utility [patent_app_number] => 17/149136 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149136
Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation Jan 13, 2021 Issued
Array ( [id] => 18292160 [patent_doc_number] => 11621033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Techniques for low power operation [patent_app_type] => utility [patent_app_number] => 17/145066 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13204 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145066
Techniques for low power operation Jan 7, 2021 Issued
Array ( [id] => 18236201 [patent_doc_number] => 11600769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => High density spin orbit torque magnetic random access memory [patent_app_type] => utility [patent_app_number] => 17/145126 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145126
High density spin orbit torque magnetic random access memory Jan 7, 2021 Issued
Array ( [id] => 16872667 [patent_doc_number] => 20210166134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => Home Wireless Discovery [patent_app_type] => utility [patent_app_number] => 17/135596 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135596
Home wireless discovery Dec 27, 2020 Issued
Array ( [id] => 17438729 [patent_doc_number] => 11264069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Apparatus with a calibration mechanism [patent_app_type] => utility [patent_app_number] => 17/131156 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9328 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131156
Apparatus with a calibration mechanism Dec 21, 2020 Issued
Array ( [id] => 17144976 [patent_doc_number] => 20210312989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/126933 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126933
Nonvolatile memory device and operation method thereof Dec 17, 2020 Issued
Array ( [id] => 17691853 [patent_doc_number] => 20220199146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS [patent_app_type] => utility [patent_app_number] => 17/125095 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125095
Apparatuses and methods for input buffer power savings Dec 16, 2020 Issued
Array ( [id] => 17529682 [patent_doc_number] => 11302380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Memory controller device and phase calibration method [patent_app_type] => utility [patent_app_number] => 17/120344 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120344
Memory controller device and phase calibration method Dec 13, 2020 Issued
Array ( [id] => 17925703 [patent_doc_number] => 11468963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Memory device and read method thereof [patent_app_type] => utility [patent_app_number] => 17/115412 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4602 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115412
Memory device and read method thereof Dec 7, 2020 Issued
Array ( [id] => 16781428 [patent_doc_number] => 20210118507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => LAYOUT PATTERN OF TWO-PORT TERNARY CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/114373 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114373
Layout pattern of two-port ternary content addressable memory Dec 6, 2020 Issued
Array ( [id] => 16723493 [patent_doc_number] => 20210090640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => CIRCUIT FOR REDUCING LEAKAGE CURRENT OF SRAM MEMORY ARRAY AND CONTROL METHOD FOR SAME [patent_app_type] => utility [patent_app_number] => 17/111379 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111379
Circuit for reducing leakage current of SRAM memory array and control method for same Dec 2, 2020 Issued
Array ( [id] => 17353003 [patent_doc_number] => 11227647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/106242 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106242
Semiconductor device Nov 29, 2020 Issued
Array ( [id] => 17683219 [patent_doc_number] => 11367480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Memory device implementing multiple port read [patent_app_type] => utility [patent_app_number] => 17/104953 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104953
Memory device implementing multiple port read Nov 24, 2020 Issued
Array ( [id] => 17636928 [patent_doc_number] => 11347652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Banked memory architecture for multiple parallel datapath channels in an accelerator [patent_app_type] => utility [patent_app_number] => 17/097205 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097205
Banked memory architecture for multiple parallel datapath channels in an accelerator Nov 12, 2020 Issued
Array ( [id] => 17485666 [patent_doc_number] => 20220093170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => DUAL-PORT SRAM CELL AND LAYOUT STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 17/098186 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098186
Dual-port SRAM cell and layout structure thereof Nov 12, 2020 Issued
Array ( [id] => 17956160 [patent_doc_number] => 11482273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Strobe tree circuit for capturing data using a memory-sourced strobe [patent_app_type] => utility [patent_app_number] => 17/095592 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8049 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095592
Strobe tree circuit for capturing data using a memory-sourced strobe Nov 10, 2020 Issued
Array ( [id] => 17283918 [patent_doc_number] => 11200958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Memories for mitigating program disturb [patent_app_type] => utility [patent_app_number] => 17/091379 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10786 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/091379
Memories for mitigating program disturb Nov 5, 2020 Issued
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