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Huedung Xuan Cao Mancuso

Examiner (ID: 153, Phone: (571)272-1939 , Office: P/2845 )

Most Active Art Unit
2821
Art Unit(s)
2772, 2671, 2821, 2845
Total Applications
1508
Issued Applications
1276
Pending Applications
51
Abandoned Applications
190

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17907790 [patent_doc_number] => 11461645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Initialization of memory networks [patent_app_type] => utility [patent_app_number] => 16/699814 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699814
Initialization of memory networks Dec 1, 2019 Issued
Array ( [id] => 17237677 [patent_doc_number] => 11181552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Categorization of acquired data based on explicit and implicit means [patent_app_type] => utility [patent_app_number] => 16/695795 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695795
Categorization of acquired data based on explicit and implicit means Nov 25, 2019 Issued
Array ( [id] => 15967773 [patent_doc_number] => 20200167638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => CIRCUIT NEURONAL APTE A METTRE EN OEUVRE UN APPRENTISSAGE SYNAPTIQUE [patent_app_type] => utility [patent_app_number] => 16/695588 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695588
CIRCUIT NEURONAL APTE A METTRE EN OEUVRE UN APPRENTISSAGE SYNAPTIQUE Nov 25, 2019 Abandoned
Array ( [id] => 15745253 [patent_doc_number] => 20200111516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => APPARATUS WITH A CALIBRATION MECHANISM [patent_app_type] => utility [patent_app_number] => 16/692306 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692306
Apparatus with a calibration mechanism Nov 21, 2019 Issued
Array ( [id] => 17106340 [patent_doc_number] => 11126557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Apparatuses and methods for cache operations [patent_app_type] => utility [patent_app_number] => 16/679553 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 25116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679553 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679553
Apparatuses and methods for cache operations Nov 10, 2019 Issued
Array ( [id] => 16826539 [patent_doc_number] => 20210141832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => STORAGE OPTIMIZATION FOR PRODUCTS MANUFACTURING [patent_app_type] => utility [patent_app_number] => 16/676496 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676496
Storage optimization for products manufacturing Nov 6, 2019 Issued
Array ( [id] => 17238428 [patent_doc_number] => 11182308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Semiconductor device with secure access key and associated methods and systems [patent_app_type] => utility [patent_app_number] => 16/677478 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 17710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677478 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677478
Semiconductor device with secure access key and associated methods and systems Nov 6, 2019 Issued
Array ( [id] => 16879975 [patent_doc_number] => 11030124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Semiconductor device with secure access key and associated methods and systems [patent_app_type] => utility [patent_app_number] => 16/677376 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 17707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677376
Semiconductor device with secure access key and associated methods and systems Nov 6, 2019 Issued
Array ( [id] => 17351583 [patent_doc_number] => 11226213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Capacitive proximity sensor [patent_app_type] => utility [patent_app_number] => 16/665131 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5823 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16665131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/665131
Capacitive proximity sensor Oct 27, 2019 Issued
Array ( [id] => 15503975 [patent_doc_number] => 20200052176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => INTERCONNECTION BY LATERAL TRANSFER PRINTING [patent_app_type] => utility [patent_app_number] => 16/660776 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660776 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660776
Interconnection by lateral transfer printing Oct 21, 2019 Issued
Array ( [id] => 16193920 [patent_doc_number] => 20200234769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/657104 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657104
Memory and operation method thereof Oct 17, 2019 Issued
Array ( [id] => 16659119 [patent_doc_number] => 20210055756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => CONNECTION INTERFACE CIRCUIT, MEMORY STORAGE DEVICE AND SIGNAL GENERATION METHOD [patent_app_type] => utility [patent_app_number] => 16/656524 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656524
Connection interface circuit, memory storage device and signal generation method Oct 16, 2019 Issued
Array ( [id] => 15837679 [patent_doc_number] => 20200134122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => INTEGRATED CIRCUIT FIN LAYOUT METHOD, SYSTEM, AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/599552 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599552
Integrated circuit fin layout method, system, and structure Oct 10, 2019 Issued
Array ( [id] => 15462283 [patent_doc_number] => 20200043966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => IMAGING PIXELS WITH PLASMONIC COLOR FILTER ELEMENTS [patent_app_type] => utility [patent_app_number] => 16/598284 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598284
Imaging pixels with plasmonic color filter elements Oct 9, 2019 Issued
Array ( [id] => 15744193 [patent_doc_number] => 20200110985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => ARTIFICAL NEURAL NETWORK CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/589415 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589415
Artificial neural network circuit Sep 30, 2019 Issued
Array ( [id] => 16331323 [patent_doc_number] => 20200302289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => USING QUANTIZATION IN TRAINING AN ARTIFICIAL INTELLIGENCE MODEL IN A SEMICONDUCTOR SOLUTION [patent_app_type] => utility [patent_app_number] => 16/586467 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586467 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586467
Using quantization in training an artificial intelligence model in a semiconductor solution Sep 26, 2019 Issued
Array ( [id] => 15656391 [patent_doc_number] => 20200090726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/583033 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583033
Redundancy array column decoder for memory Sep 24, 2019 Issued
Array ( [id] => 16256528 [patent_doc_number] => 20200265903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/578928 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578928
Memory system and method of operating the same Sep 22, 2019 Issued
Array ( [id] => 18704462 [patent_doc_number] => 11790978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Register file with write pre-charge [patent_app_type] => utility [patent_app_number] => 16/578992 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9322 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578992
Register file with write pre-charge Sep 22, 2019 Issued
Array ( [id] => 16668232 [patent_doc_number] => 10937485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Redundant voltage regulator for memory devices [patent_app_type] => utility [patent_app_number] => 16/577644 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577644
Redundant voltage regulator for memory devices Sep 19, 2019 Issued
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