Huedung Xuan Cao Mancuso

Array ( [id] => 19866013 [patent_doc_number] => 20250104799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MIXED-MODE VIRTUAL BLOCK GENERATION [patent_app_type] => utility [patent_app_number] => 18/788730 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19589532 [patent_doc_number] => 20240387089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SYNTHETIC ANTIFERROMAGNET, MAGNETIC TUNNELING JUNCTION DEVICE INCLUDING THE SYNTHETIC ANTIFERROMAGNET, AND MEMORY DEVICE INCLUDING THE MAGNETIC TUNNELING JUNCTION DEVICE [patent_app_type] => utility [patent_app_number] => 18/785018 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19835491 [patent_doc_number] => 20250087277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => ALTERNATIVE ERASE SCHEMES FOR RELIABILITY-RISK WORD LINES [patent_app_type] => utility [patent_app_number] => 18/784022 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20002098 [patent_doc_number] => 20250140320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => OPERATIONS ON PARTIALLY PROGRAMMED ERASE BLOCKS [patent_app_type] => utility [patent_app_number] => 18/784434 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20235519 [patent_doc_number] => 20250292838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/776549 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19559628 [patent_doc_number] => 20240371420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DEVICE AND METHOD FOR READING DATA IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/776720 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20731732 [patent_doc_number] => 12638990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Second read initialization on latch-limited memory device [patent_app_type] => utility [patent_app_number] => 18/768806 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20448127 [patent_doc_number] => 20260004852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => SUSPEND-RESUME-GO TECHNIQUES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/757857 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19531476 [patent_doc_number] => 20240355378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS [patent_app_type] => utility [patent_app_number] => 18/758749 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19687726 [patent_doc_number] => 20250006271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MEMORY ARRAY CIRCUIT, TERNARY CONTENT ADDRESSABLE MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/755664 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20448144 [patent_doc_number] => 20260004869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => LINK STRESS PATTERN TO ENSURE COMMAND ADDRESS BUS INTEGRITY [patent_app_type] => utility [patent_app_number] => 18/755394 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20429375 [patent_doc_number] => 20250391468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => NOR DECODER FOR LARGE DECODE STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/749799 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20746628 [patent_doc_number] => 12646547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/749367 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 8599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500420 [patent_doc_number] => 20240339438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => STACKED SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/747448 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500116 [patent_doc_number] => 20240339134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => STACKED SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/746052 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20086940 [patent_doc_number] => 20250216876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => METHOD OF STABILIZING OUTPUT VOLTAGE OF VOLTAGE REGULATOR, ELECTRONIC DEVICE AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/747033 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19943426 [patent_doc_number] => 12315562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => RRAM circuit and method [patent_app_type] => utility [patent_app_number] => 18/743997 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500529 [patent_doc_number] => 20240339547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => FLASH MEMORY DEVICE AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/742191 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20409786 [patent_doc_number] => 20250378895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => IN-PLACE READ REFRESH TECHNIQUES FOR NONVOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/737819 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19634332 [patent_doc_number] => 20240412781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => COMPUTE-IN-MEMORY PROCESSOR SUPPORTING BOTH GENERAL-PURPOSE CPU AND DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 18/737007 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737007 [rel_patent_id] =>[rel_patent_doc_number] =>)