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Huedung Xuan Cao Mancuso

Examiner (ID: 153, Phone: (571)272-1939 , Office: P/2845 )

Most Active Art Unit
2821
Art Unit(s)
2772, 2671, 2821, 2845
Total Applications
1508
Issued Applications
1276
Pending Applications
51
Abandoned Applications
190

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19160842 [patent_doc_number] => 20240153549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => 2-PORT SRAM COMPRISING A CFET [patent_app_type] => utility [patent_app_number] => 18/413959 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413959
2-port SRAM comprising a CFET Jan 15, 2024 Issued
Array ( [id] => 20673142 [patent_doc_number] => 12613653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Low pass through voltage on lower tier wordlines for read disturb improvement [patent_app_type] => utility [patent_app_number] => 18/412010 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9979 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412010
Low pass through voltage on lower tier wordlines for read disturb improvement Jan 11, 2024 Issued
Array ( [id] => 20611018 [patent_doc_number] => 12586622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Digital device having a reset pad circuit that may be subject to hacker attack [patent_app_type] => utility [patent_app_number] => 18/410049 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2047 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410049
Digital device having a reset pad circuit that may be subject to hacker attack Jan 10, 2024 Issued
Array ( [id] => 19866009 [patent_doc_number] => 20250104795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY DEVICE, AND MEMORY SYSTEM AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/409241 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409241 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409241
Memory device, and memory system and operation method thereof Jan 9, 2024 Issued
Array ( [id] => 19993728 [patent_doc_number] => 20250131950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => MEMORY DEVICES, OPERATION METHODS THEREOF, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/409430 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409430
Memory devices, operation methods thereof, and memory systems Jan 9, 2024 Issued
Array ( [id] => 19466247 [patent_doc_number] => 20240319917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/409481 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409481
Memory system Jan 9, 2024 Issued
Array ( [id] => 20389125 [patent_doc_number] => 12488858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Method and circuitry for handling defective memory cells and wordlines in memory module [patent_app_type] => utility [patent_app_number] => 18/404853 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404853
Method and circuitry for handling defective memory cells and wordlines in memory module Jan 3, 2024 Issued
Array ( [id] => 19221211 [patent_doc_number] => 20240185915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => OPTIMIZATION OF SOFT BIT WINDOWS BASED ON SIGNAL AND NOISE CHARACTERISTICS OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/404225 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404225 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404225
Optimization of soft bit windows based on signal and noise characteristics of memory cells Jan 3, 2024 Issued
Array ( [id] => 20538563 [patent_doc_number] => 12555642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Architecture and method for NAND memory operation [patent_app_type] => utility [patent_app_number] => 18/404742 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404742 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404742
Architecture and method for NAND memory operation Jan 3, 2024 Issued
Array ( [id] => 19071303 [patent_doc_number] => 20240105729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/534689 [patent_app_country] => US [patent_app_date] => 2023-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 107761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534689
Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells Dec 9, 2023 Issued
Array ( [id] => 20440396 [patent_doc_number] => 12511232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Trim setting determination on a memory device [patent_app_type] => utility [patent_app_number] => 18/528375 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528375
Trim setting determination on a memory device Dec 3, 2023 Issued
Array ( [id] => 20345819 [patent_doc_number] => 12469554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Devices, chips, and electronic equipment for sensing-memory-computing synergy [patent_app_type] => utility [patent_app_number] => 18/521746 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4499 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521746 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521746
Devices, chips, and electronic equipment for sensing-memory-computing synergy Nov 27, 2023 Issued
Array ( [id] => 20274675 [patent_doc_number] => 12444459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Memory device and method for adjusting logic states of data strobe signals used by memory device [patent_app_type] => utility [patent_app_number] => 18/520135 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4952 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520135 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520135
Memory device and method for adjusting logic states of data strobe signals used by memory device Nov 26, 2023 Issued
Array ( [id] => 20266827 [patent_doc_number] => 12437823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Memory device and reading method thereof [patent_app_type] => utility [patent_app_number] => 18/519201 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 5256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519201
Memory device and reading method thereof Nov 26, 2023 Issued
Array ( [id] => 20034864 [patent_doc_number] => 20250173086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/519051 [patent_app_country] => US [patent_app_date] => 2023-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519051 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519051
Memory device Nov 25, 2023 Issued
Array ( [id] => 19559627 [patent_doc_number] => 20240371419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM CAPABLE OF PERFORMING A TRAINING OPERATION [patent_app_type] => utility [patent_app_number] => 18/518035 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518035
Semiconductor apparatus and a semiconductor system capable of performing a training operation Nov 21, 2023 Issued
Array ( [id] => 19036797 [patent_doc_number] => 20240086612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => INTEGRATED CIRCUIT FIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/517400 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18517400 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/517400
Integrated circuit fin structure Nov 21, 2023 Issued
Array ( [id] => 20783832 [patent_doc_number] => 20260172035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-18 [patent_title] => DELAY BUFFER UNIT AND OPERATING METHOD THEREOF, COMPUTING DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/716127 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18716127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/716127
DELAY BUFFER UNIT AND OPERATING METHOD THEREOF, COMPUTING DEVICE AND OPERATING METHOD THEREOF Nov 15, 2023 Pending
Array ( [id] => 20243957 [patent_doc_number] => 12424287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions [patent_app_type] => utility [patent_app_number] => 18/507387 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 10572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/507387
Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions Nov 12, 2023 Issued
Array ( [id] => 19711102 [patent_doc_number] => 20250021244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => STORAGE DEVICE ENTERING LOW POWER MODE AFTER EXECUTING BACKGROUND OPERATION AND OPERATING METHOD OF THE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/505113 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505113
Storage device entering low power mode after executing background operation and operating method of the storage device Nov 8, 2023 Issued
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