Search

Hung K. Vu

Examiner (ID: 9736)

Most Active Art Unit
2897
Art Unit(s)
2811, 2897
Total Applications
1874
Issued Applications
1571
Pending Applications
97
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19618920 [patent_doc_number] => 20240404600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH SLITS [patent_app_type] => utility [patent_app_number] => 18/800057 [patent_app_country] => US [patent_app_date] => 2024-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/800057
3D semiconductor devices and structures with slits Aug 9, 2024 Issued
Array ( [id] => 19500414 [patent_doc_number] => 20240339432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => JOINT STRUCTURE IN SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/749542 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749542
Joint structure in semiconductor package and manufacturing method thereof Jun 19, 2024 Issued
Array ( [id] => 19500439 [patent_doc_number] => 20240339457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => CONTAMINANT COLLECTION ON SOI [patent_app_type] => utility [patent_app_number] => 18/748862 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748862 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748862
CONTAMINANT COLLECTION ON SOI Jun 19, 2024 Pending
Array ( [id] => 19589939 [patent_doc_number] => 20240387496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/738281 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738281
Systems and methods for assembling processor systems Jun 9, 2024 Issued
Array ( [id] => 20305465 [patent_doc_number] => 12451466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Edge interface placements to enable chiplet rotation into multi-chiplet cluster [patent_app_type] => utility [patent_app_number] => 18/734765 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1155 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734765 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734765
Edge interface placements to enable chiplet rotation into multi-chiplet cluster Jun 4, 2024 Issued
Array ( [id] => 20161368 [patent_doc_number] => 12388003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Chip package structure with metal-containing layer [patent_app_type] => utility [patent_app_number] => 18/675785 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 3135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675785
Chip package structure with metal-containing layer May 27, 2024 Issued
Array ( [id] => 19452809 [patent_doc_number] => 20240312939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/674950 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674950
Semiconductor device May 26, 2024 Issued
Array ( [id] => 19436035 [patent_doc_number] => 20240304533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => BUMP JOINT STRUCTURE WITH DISTORTION AND METHOD FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/668922 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668922
Bump joint structure with distortion and method forming same May 19, 2024 Issued
Array ( [id] => 19422364 [patent_doc_number] => 20240298488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => DISPLAY PANEL AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/661658 [patent_app_country] => US [patent_app_date] => 2024-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661658 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661658
Display panel and display apparatus May 11, 2024 Issued
Array ( [id] => 20111514 [patent_doc_number] => 12362250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Protruding SN substrate features for epoxy flow control [patent_app_type] => utility [patent_app_number] => 18/632047 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 1044 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632047
Protruding SN substrate features for epoxy flow control Apr 9, 2024 Issued
Array ( [id] => 19349302 [patent_doc_number] => 20240258266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 18/629670 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629670
Package bonding structures and method of formation Apr 7, 2024 Issued
Array ( [id] => 19619272 [patent_doc_number] => 20240404952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => FLIP-CHIP SEMICONDUCTOR-ON-INSULATOR TRANSISTOR LAYOUT [patent_app_type] => utility [patent_app_number] => 18/618432 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618432
Flip-chip semiconductor-on-insulator transistor layout Mar 26, 2024 Issued
Array ( [id] => 20111493 [patent_doc_number] => 12362229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor device structures [patent_app_type] => utility [patent_app_number] => 18/603483 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 2034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603483 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603483
Semiconductor device structures Mar 12, 2024 Issued
Array ( [id] => 19582573 [patent_doc_number] => 12148701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/594816 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7604 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594816 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594816
Semiconductor device Mar 3, 2024 Issued
Array ( [id] => 19223750 [patent_doc_number] => 20240188454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => METAL LANDING ON TOP ELECTRODE OF RRAM [patent_app_type] => utility [patent_app_number] => 18/443368 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443368
Metal landing on top electrode of RRAM Feb 15, 2024 Issued
Array ( [id] => 19221510 [patent_doc_number] => 20240186214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Three Dimensional IC Package with Thermal Enhancement [patent_app_type] => utility [patent_app_number] => 18/442845 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442845
Three Dimensional IC Package with Thermal Enhancement Feb 14, 2024 Pending
Array ( [id] => 19567810 [patent_doc_number] => 12142589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Semiconductor device including resistor element [patent_app_type] => utility [patent_app_number] => 18/432788 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6969 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432788
Semiconductor device including resistor element Feb 4, 2024 Issued
Array ( [id] => 19886933 [patent_doc_number] => 12272664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor packages having conductive pillars with inclined surfaces [patent_app_type] => utility [patent_app_number] => 18/402611 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402611
Semiconductor packages having conductive pillars with inclined surfaces Jan 1, 2024 Issued
Array ( [id] => 19912552 [patent_doc_number] => 12288771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Apparatus for non-volatile random access memory stacks [patent_app_type] => utility [patent_app_number] => 18/519538 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519538 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519538
Apparatus for non-volatile random access memory stacks Nov 26, 2023 Issued
Array ( [id] => 19038231 [patent_doc_number] => 20240088046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => Standard Cell Layout for Better Routability [patent_app_type] => utility [patent_app_number] => 18/515657 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515657
Standard cell layout for better routability Nov 20, 2023 Issued
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