
Hung K. Vu
Examiner (ID: 17056, Phone: (571)272-1666 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2811 |
| Total Applications | 1933 |
| Issued Applications | 1601 |
| Pending Applications | 110 |
| Abandoned Applications | 241 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19618920
[patent_doc_number] => 20240404600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH SLITS
[patent_app_type] => utility
[patent_app_number] => 18/800057
[patent_app_country] => US
[patent_app_date] => 2024-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 36663
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800057
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/800057 | 3D semiconductor devices and structures with slits | Aug 9, 2024 | Issued |
Array
(
[id] => 19546533
[patent_doc_number] => 20240363569
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => BUMP INTEGRATION WITH REDISTRIBUTION LAYER
[patent_app_type] => utility
[patent_app_number] => 18/763481
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8540
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763481
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/763481 | Bump integration with redistribution layer | Jul 2, 2024 | Issued |
Array
(
[id] => 19531901
[patent_doc_number] => 20240355803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/757882
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6814
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757882
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/757882 | SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME | Jun 27, 2024 | Pending |
Array
(
[id] => 19500439
[patent_doc_number] => 20240339457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => CONTAMINANT COLLECTION ON SOI
[patent_app_type] => utility
[patent_app_number] => 18/748862
[patent_app_country] => US
[patent_app_date] => 2024-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7972
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748862
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/748862 | Contaminant collection on SOI | Jun 19, 2024 | Issued |
Array
(
[id] => 19500414
[patent_doc_number] => 20240339432
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => JOINT STRUCTURE IN SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/749542
[patent_app_country] => US
[patent_app_date] => 2024-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21213
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749542
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/749542 | Joint structure in semiconductor package and manufacturing method thereof | Jun 19, 2024 | Issued |
Array
(
[id] => 19894949
[patent_doc_number] => 20250120261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/744289
[patent_app_country] => US
[patent_app_date] => 2024-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17749
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744289
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/744289 | DISPLAY DEVICE | Jun 13, 2024 | Pending |
Array
(
[id] => 19589939
[patent_doc_number] => 20240387496
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 18/738281
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8812
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738281
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/738281 | Systems and methods for assembling processor systems | Jun 9, 2024 | Issued |
Array
(
[id] => 20305465
[patent_doc_number] => 12451466
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Edge interface placements to enable chiplet rotation into multi-chiplet cluster
[patent_app_type] => utility
[patent_app_number] => 18/734765
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 1155
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734765
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/734765 | Edge interface placements to enable chiplet rotation into multi-chiplet cluster | Jun 4, 2024 | Issued |
Array
(
[id] => 20065748
[patent_doc_number] => 20250203970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => METHOD OF FORMING CFET DEVICE BY INTERPOSER LAYER REPLACEMENT AND RELATED STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/679071
[patent_app_country] => US
[patent_app_date] => 2024-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679071
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/679071 | METHOD OF FORMING CFET DEVICE BY INTERPOSER LAYER REPLACEMENT AND RELATED STRUCTURES | May 29, 2024 | Pending |
Array
(
[id] => 20161368
[patent_doc_number] => 12388003
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => Chip package structure with metal-containing layer
[patent_app_type] => utility
[patent_app_number] => 18/675785
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 3135
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675785
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675785 | Chip package structure with metal-containing layer | May 27, 2024 | Issued |
Array
(
[id] => 19452809
[patent_doc_number] => 20240312939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/674950
[patent_app_country] => US
[patent_app_date] => 2024-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5661
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674950
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/674950 | Semiconductor device | May 26, 2024 | Issued |
Array
(
[id] => 19436035
[patent_doc_number] => 20240304533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => BUMP JOINT STRUCTURE WITH DISTORTION AND METHOD FORMING SAME
[patent_app_type] => utility
[patent_app_number] => 18/668922
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7826
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668922
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/668922 | Bump joint structure with distortion and method forming same | May 19, 2024 | Issued |
Array
(
[id] => 19422364
[patent_doc_number] => 20240298488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-05
[patent_title] => DISPLAY PANEL AND DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/661658
[patent_app_country] => US
[patent_app_date] => 2024-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7103
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661658
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/661658 | Display panel and display apparatus | May 11, 2024 | Issued |
Array
(
[id] => 19407236
[patent_doc_number] => 20240290747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => IC MODULE AND METHOD FOR MANUFACTURING IC MODULE
[patent_app_type] => utility
[patent_app_number] => 18/657067
[patent_app_country] => US
[patent_app_date] => 2024-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6423
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657067
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/657067 | IC MODULE AND METHOD FOR MANUFACTURING IC MODULE | May 6, 2024 | Pending |
Array
(
[id] => 20111514
[patent_doc_number] => 12362250
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Protruding SN substrate features for epoxy flow control
[patent_app_type] => utility
[patent_app_number] => 18/632047
[patent_app_country] => US
[patent_app_date] => 2024-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 1044
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632047
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/632047 | Protruding SN substrate features for epoxy flow control | Apr 9, 2024 | Issued |
Array
(
[id] => 19349302
[patent_doc_number] => 20240258266
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 18/629670
[patent_app_country] => US
[patent_app_date] => 2024-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12887
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629670
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/629670 | Package bonding structures and method of formation | Apr 7, 2024 | Issued |
Array
(
[id] => 20283851
[patent_doc_number] => 20250309093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => POWER RAIL IN STACKED FET DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/621018
[patent_app_country] => US
[patent_app_date] => 2024-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2327
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621018
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/621018 | POWER RAIL IN STACKED FET DEVICES | Mar 27, 2024 | Pending |
Array
(
[id] => 19688011
[patent_doc_number] => 20250006556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => SELF-ALIGNED NANOMETER THROUGH-SILICON-VIA STRUCTURE AND METHOD OF PREPARING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/618706
[patent_app_country] => US
[patent_app_date] => 2024-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9116
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 696
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618706
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/618706 | SELF-ALIGNED NANOMETER THROUGH-SILICON-VIA STRUCTURE AND METHOD OF PREPARING THE SAME | Mar 26, 2024 | Pending |
Array
(
[id] => 19619272
[patent_doc_number] => 20240404952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => FLIP-CHIP SEMICONDUCTOR-ON-INSULATOR TRANSISTOR LAYOUT
[patent_app_type] => utility
[patent_app_number] => 18/618432
[patent_app_country] => US
[patent_app_date] => 2024-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19725
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618432
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/618432 | Flip-chip semiconductor-on-insulator transistor layout | Mar 26, 2024 | Issued |
Array
(
[id] => 19479161
[patent_doc_number] => 20240327203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => METHOD FOR MANUFACTURING A MEMS TRANSDUCER DEVICE WITH THIN MEMBRANE, AND MEMS TRANSDUCER DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/613746
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9403
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613746
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/613746 | METHOD FOR MANUFACTURING A MEMS TRANSDUCER DEVICE WITH THIN MEMBRANE, AND MEMS TRANSDUCER DEVICE | Mar 21, 2024 | Pending |