Search

Hung K. Vu

Examiner (ID: 9736)

Most Active Art Unit
2897
Art Unit(s)
2811, 2897
Total Applications
1874
Issued Applications
1571
Pending Applications
97
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19108682 [patent_doc_number] => 11961796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Semiconductor package dielectric substrate including a trench [patent_app_type] => utility [patent_app_number] => 17/461828 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461828
Semiconductor package dielectric substrate including a trench Aug 29, 2021 Issued
Array ( [id] => 17339490 [patent_doc_number] => 20220005821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => 3D MEMORY SEMICONDUCTOR DEVICE AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/461075 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461075
3D memory semiconductor device and structure Aug 29, 2021 Issued
Array ( [id] => 18579124 [patent_doc_number] => 11735664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Source/drain regions of FINFET devices and methods of forming same [patent_app_type] => utility [patent_app_number] => 17/460453 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 8554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460453
Source/drain regions of FINFET devices and methods of forming same Aug 29, 2021 Issued
Array ( [id] => 17295467 [patent_doc_number] => 20210391306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => METHODS OF FORMING INTEGRATED CIRCUIT PACKAGES [patent_app_type] => utility [patent_app_number] => 17/458549 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458549
Methods of forming integrated circuit packages Aug 26, 2021 Issued
Array ( [id] => 19356967 [patent_doc_number] => 12057424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Package structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/411701 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 10487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411701
Package structure and method for forming the same Aug 24, 2021 Issued
Array ( [id] => 17751382 [patent_doc_number] => 20220229587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/408772 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408772 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408772
Memory system Aug 22, 2021 Issued
Array ( [id] => 18211121 [patent_doc_number] => 20230057384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => HYBRID CARRIER FOR ELECTRONIC SUBSTRATE TECHNOLOGIES [patent_app_type] => utility [patent_app_number] => 17/408157 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408157
HYBRID CARRIER FOR ELECTRONIC SUBSTRATE TECHNOLOGIES Aug 19, 2021 Pending
Array ( [id] => 17448275 [patent_doc_number] => 20220068780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => INTEGRATED CIRCUIT (IC) PACKAGE SUBSTRATE WITH EMBEDDED TRACE SUBSTRATE (ETS) LAYER ON A SUBSTRATE, AND RELATED FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/405494 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405494
Integrated circuit (IC) package substrate with embedded trace substrate (ETS) layer on a substrate, and related fabrication methods Aug 17, 2021 Issued
Array ( [id] => 18416028 [patent_doc_number] => 11670575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Package structure, RDL structure comprising redistribution layer having ground plates and signal lines [patent_app_type] => utility [patent_app_number] => 17/395450 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395450
Package structure, RDL structure comprising redistribution layer having ground plates and signal lines Aug 4, 2021 Issued
Array ( [id] => 17870790 [patent_doc_number] => 20220293527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/383338 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17383338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/383338
Semiconductor packages with interconnection features in a seal region and methods for forming the same Jul 21, 2021 Issued
Array ( [id] => 19314436 [patent_doc_number] => 12040262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Flex board and flexible module [patent_app_type] => utility [patent_app_number] => 17/381931 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 5598 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381931
Flex board and flexible module Jul 20, 2021 Issued
Array ( [id] => 18343451 [patent_doc_number] => 11640935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/377395 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 9947 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377395
Semiconductor package and manufacturing method thereof Jul 15, 2021 Issued
Array ( [id] => 17359927 [patent_doc_number] => 20220020723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => CHIP-CARRYING STRUCTURE AND CHIP-BONDING METHOD [patent_app_type] => utility [patent_app_number] => 17/373876 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373876
CHIP-CARRYING STRUCTURE AND CHIP-BONDING METHOD Jul 12, 2021 Abandoned
Array ( [id] => 18317685 [patent_doc_number] => 11631771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Oxide semiconductor field effect transistor [patent_app_type] => utility [patent_app_number] => 17/367637 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3216 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367637
Oxide semiconductor field effect transistor Jul 5, 2021 Issued
Array ( [id] => 18343502 [patent_doc_number] => 11640986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Implantation and annealing for semiconductor device [patent_app_type] => utility [patent_app_number] => 17/363645 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 7526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363645
Implantation and annealing for semiconductor device Jun 29, 2021 Issued
Array ( [id] => 18113000 [patent_doc_number] => 20230005880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => FLIP CHIP PACKAGED DEVICES WITH THERMAL PAD [patent_app_type] => utility [patent_app_number] => 17/364735 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364735 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364735
Flip chip packaged devices with thermal pad Jun 29, 2021 Issued
Array ( [id] => 18751511 [patent_doc_number] => 11810832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Heat sink configuration for multi-chip module [patent_app_type] => utility [patent_app_number] => 17/360571 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360571
Heat sink configuration for multi-chip module Jun 27, 2021 Issued
Array ( [id] => 18081149 [patent_doc_number] => 20220406761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => THERMAL MANAGEMENT FOR PACKAGE ON PACKAGE ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/354078 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/354078
Thermal management for package on package assembly Jun 21, 2021 Issued
Array ( [id] => 17145451 [patent_doc_number] => 20210313464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => LOW-CAPACITANCE STRUCTURES AND PROCESSES [patent_app_type] => utility [patent_app_number] => 17/353089 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353089 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353089
Low-capacitance structures and processes Jun 20, 2021 Issued
Array ( [id] => 18520816 [patent_doc_number] => 11710711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Integrated circuit provided with decoys against reverse engineering and corresponding fabrication process [patent_app_type] => utility [patent_app_number] => 17/351930 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 4507 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351930
Integrated circuit provided with decoys against reverse engineering and corresponding fabrication process Jun 17, 2021 Issued
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