Search

Hung K. Vu

Examiner (ID: 9736)

Most Active Art Unit
2897
Art Unit(s)
2811, 2897
Total Applications
1874
Issued Applications
1571
Pending Applications
97
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20188218 [patent_doc_number] => 12399328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Automated fiber optic interconnection system based on non repeating braid algorithm, robot, and fixed, identical length optical fibers [patent_app_type] => utility [patent_app_number] => 17/100830 [patent_app_country] => US [patent_app_date] => 2020-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1882 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100830
Automated fiber optic interconnection system based on non repeating braid algorithm, robot, and fixed, identical length optical fibers Nov 20, 2020 Issued
Array ( [id] => 18140805 [patent_doc_number] => 20230014646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/781912 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/781912
SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS Nov 18, 2020 Pending
Array ( [id] => 18140805 [patent_doc_number] => 20230014646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/781912 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/781912
SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS Nov 18, 2020 Pending
Array ( [id] => 18140805 [patent_doc_number] => 20230014646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/781912 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/781912
SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS Nov 18, 2020 Pending
Array ( [id] => 18140805 [patent_doc_number] => 20230014646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/781912 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17781912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/781912
SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS Nov 18, 2020 Pending
Array ( [id] => 19328856 [patent_doc_number] => 12046545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Hybrid reconstituted substrate for electronic packaging [patent_app_type] => utility [patent_app_number] => 17/093090 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3415 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093090
Hybrid reconstituted substrate for electronic packaging Nov 8, 2020 Issued
Array ( [id] => 17599415 [patent_doc_number] => 20220148989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 17/092195 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092195
Semiconductor packages Nov 5, 2020 Issued
Array ( [id] => 16776111 [patent_doc_number] => 20210113188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => VERTICAL PACKAGING FOR ULTRASOUND-ON-A-CHIP AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/088336 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088336
Vertical packaging for ultrasound-on-a-chip and related methods Nov 2, 2020 Issued
Array ( [id] => 18061970 [patent_doc_number] => 20220393057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => CHARGED-PARTICLE DETECTOR PACKAGE FOR HIGH SPEED APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/774130 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17774130 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/774130
CHARGED-PARTICLE DETECTOR PACKAGE FOR HIGH SPEED APPLICATIONS Oct 29, 2020 Pending
Array ( [id] => 17529913 [patent_doc_number] => 11302612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Lead frame wiring structure and semiconductor module [patent_app_type] => utility [patent_app_number] => 17/085758 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7425 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085758
Lead frame wiring structure and semiconductor module Oct 29, 2020 Issued
Array ( [id] => 19260996 [patent_doc_number] => 12021062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Edge interface placements to enable chiplet rotation into multi-chiplet cluster [patent_app_type] => utility [patent_app_number] => 17/075117 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6645 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075117
Edge interface placements to enable chiplet rotation into multi-chiplet cluster Oct 19, 2020 Issued
Array ( [id] => 19494330 [patent_doc_number] => 12113054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Non-volatile dynamic random access memory [patent_app_type] => utility [patent_app_number] => 17/070253 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4321 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070253
Non-volatile dynamic random access memory Oct 13, 2020 Issued
Array ( [id] => 16631792 [patent_doc_number] => 20210050445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => TRANSISTORS WITH DUAL WELLS [patent_app_type] => utility [patent_app_number] => 17/070097 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070097
TRANSISTORS WITH DUAL WELLS Oct 13, 2020 Abandoned
Array ( [id] => 17536739 [patent_doc_number] => 20220115348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => 3D MODIFIED SURFACE TO ENABLE IMPROVED BOND STRENGTH AND YIELD OF ELECTRICAL INTERCONNECTIONS [patent_app_type] => utility [patent_app_number] => 17/067955 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067955
3D MODIFIED SURFACE TO ENABLE IMPROVED BOND STRENGTH AND YIELD OF ELECTRICAL INTERCONNECTIONS Oct 11, 2020 Abandoned
Array ( [id] => 16765561 [patent_doc_number] => 20210111143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/062685 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062685
Semiconductor device and method for fabricating a semiconductor device Oct 4, 2020 Issued
Array ( [id] => 17818592 [patent_doc_number] => 11424216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Electronic device bonding structure and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/030380 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5980 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030380
Electronic device bonding structure and fabrication method thereof Sep 23, 2020 Issued
Array ( [id] => 16561018 [patent_doc_number] => 20210006167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME [patent_app_type] => utility [patent_app_number] => 17/029302 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029302
MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME Sep 22, 2020 Abandoned
Array ( [id] => 18688415 [patent_doc_number] => 11784160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Asymmetric die bonding [patent_app_type] => utility [patent_app_number] => 17/030360 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030360
Asymmetric die bonding Sep 22, 2020 Issued
Array ( [id] => 16723915 [patent_doc_number] => 20210091062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/026740 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026740
Systems and methods for assembling processor systems Sep 20, 2020 Issued
Array ( [id] => 16529104 [patent_doc_number] => 20200403185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/015145 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015145
Semiconductor device Sep 8, 2020 Issued
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