Search

Hung K. Vu

Examiner (ID: 17056, Phone: (571)272-1666 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2811
Total Applications
1933
Issued Applications
1601
Pending Applications
110
Abandoned Applications
241

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20926088 [patent_doc_number] => 12721178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Magnetic shielding for magneto resistive memory [patent_app_type] => utility [patent_app_number] => 18/295518 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295518 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295518
MAGNETIC SHIELDING FOR MAGNETO RESISTIVE MEMORY Apr 3, 2023 Pending
Array ( [id] => 19484171 [patent_doc_number] => 20240332213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => PROTRUDED SCRIBE FEATURE DELAMINATION MITIGATION [patent_app_type] => utility [patent_app_number] => 18/194512 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194512
Protruded scribe feature delamination mitigation Mar 30, 2023 Issued
Array ( [id] => 19484083 [patent_doc_number] => 20240332125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => 2D FILLERS FOR REDUCED CTE FOR PID [patent_app_type] => utility [patent_app_number] => 18/128848 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18128848 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/128848
2D FILLERS FOR REDUCED CTE FOR PID Mar 29, 2023 Pending
Array ( [id] => 18680044 [patent_doc_number] => 20230317702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => Large-Scale Interleaved Transmitters and Receivers Heterogeneously Integrated on a Common Substrate [patent_app_type] => utility [patent_app_number] => 18/191308 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191308
Large-Scale Interleaved Transmitters and Receivers Heterogeneously Integrated on a Common Substrate Mar 27, 2023 Abandoned
Array ( [id] => 19269500 [patent_doc_number] => 20240213204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => CIRCUIT BOARD, MANUFACTURING METHOD THEREOF, AND ELECTRONIC COMPONENT PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/127235 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18127235 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/127235
Circuit board, manufacturing method thereof, and electronic component package including the same Mar 27, 2023 Issued
Array ( [id] => 19654482 [patent_doc_number] => 12176282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Manufacturing method of semiconductor package [patent_app_type] => utility [patent_app_number] => 18/190935 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 9996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190935
Manufacturing method of semiconductor package Mar 26, 2023 Issued
Array ( [id] => 19943682 [patent_doc_number] => 12315818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Interconnection structure of a semiconductor chip having pads of different widths and semiconductor package including the interconnection structure [patent_app_type] => utility [patent_app_number] => 18/126759 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 3183 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126759
Interconnection structure of a semiconductor chip having pads of different widths and semiconductor package including the interconnection structure Mar 26, 2023 Issued
Array ( [id] => 20532336 [patent_doc_number] => 12550790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Stacked integrated circuit (IC) package [patent_app_type] => utility [patent_app_number] => 18/184029 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184029
Stacked integrated circuit (IC) package Mar 14, 2023 Issued
Array ( [id] => 20334468 [patent_doc_number] => 12464764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Low parasitic capacitance contact structure [patent_app_type] => utility [patent_app_number] => 18/182910 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182910 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182910
Low parasitic capacitance contact structure Mar 12, 2023 Issued
Array ( [id] => 18759837 [patent_doc_number] => 11810876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-07 [patent_title] => Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits [patent_app_type] => utility [patent_app_number] => 18/182314 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182314 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182314
Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits Mar 9, 2023 Issued
Array ( [id] => 19837675 [patent_doc_number] => 20250089461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => Display Substrate and Display Device [patent_app_type] => utility [patent_app_number] => 18/289099 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18289099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/289099
Display Substrate and Display Device Feb 26, 2023 Pending
Array ( [id] => 18458806 [patent_doc_number] => 20230200088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/113070 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113070
Magnetoresistive random access memory and method for fabricating the same Feb 22, 2023 Issued
Array ( [id] => 19305791 [patent_doc_number] => 20240234371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/171672 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171672
CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Feb 20, 2023 Pending
Array ( [id] => 18424193 [patent_doc_number] => 20230178657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/103505 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103505
Oxide semiconductor field effect transistor Jan 30, 2023 Issued
Array ( [id] => 20470978 [patent_doc_number] => 12527024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Transistors with dual wells [patent_app_type] => utility [patent_app_number] => 18/102833 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/102833
Transistors with dual wells Jan 29, 2023 Issued
Array ( [id] => 19371752 [patent_doc_number] => 12063857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Organic light-emitting device and display apparatus including the same [patent_app_type] => utility [patent_app_number] => 18/160631 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 21658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160631
Organic light-emitting device and display apparatus including the same Jan 26, 2023 Issued
Array ( [id] => 18381984 [patent_doc_number] => 20230157075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/098740 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098740 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098740
Display device Jan 18, 2023 Issued
Array ( [id] => 20244117 [patent_doc_number] => 12424448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Reduction of line wiggling [patent_app_type] => utility [patent_app_number] => 18/156123 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156123
Reduction of line wiggling Jan 17, 2023 Issued
Array ( [id] => 18362653 [patent_doc_number] => 20230144244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 18/153532 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153532
Semiconductor Device and Method of Manufacture Jan 11, 2023 Pending
Array ( [id] => 18352278 [patent_doc_number] => 20230140389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 18/091781 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091781 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091781
Multi-chip package with high density interconnects Dec 29, 2022 Issued
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