Search

Hung K. Vu

Examiner (ID: 17056, Phone: (571)272-1666 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2811
Total Applications
1933
Issued Applications
1601
Pending Applications
110
Abandoned Applications
241

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18346166 [patent_doc_number] => 20230134276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE INCLUDING UNDER-BUMP METALLURGY [patent_app_type] => utility [patent_app_number] => 18/091509 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091509
Fan-out semiconductor package including under-bump metallurgy Dec 29, 2022 Issued
Array ( [id] => 18456283 [patent_doc_number] => 20230197565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => REMOTE MECHANICAL ATTACHMENT FOR BONDED THERMAL MANAGEMENT SOLUTIONS [patent_app_type] => utility [patent_app_number] => 18/090420 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090420 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090420
REMOTE MECHANICAL ATTACHMENT FOR BONDED THERMAL MANAGEMENT SOLUTIONS Dec 27, 2022 Pending
Array ( [id] => 19285883 [patent_doc_number] => 20240222360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => INTEGRATED CIRCUIT STRUCTURES HAVING STACKED ELECTROSTATIC DISCHARGE (ESD) FOR BACKSIDE POWER DELIVERY [patent_app_type] => utility [patent_app_number] => 18/089908 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089908
INTEGRATED CIRCUIT STRUCTURES HAVING STACKED ELECTROSTATIC DISCHARGE (ESD) FOR BACKSIDE POWER DELIVERY Dec 27, 2022 Pending
Array ( [id] => 19252818 [patent_doc_number] => 20240203815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => LAYER TRANSFER DIODE OR THIN-FILM RESISTOR FOR GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/085106 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085106
LAYER TRANSFER DIODE OR THIN-FILM RESISTOR FOR GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY Dec 19, 2022 Pending
Array ( [id] => 19252872 [patent_doc_number] => 20240203869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => INTEGRATED CIRCUIT DEVICES WITH HYBRID METAL LINES [patent_app_type] => utility [patent_app_number] => 18/067031 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067031 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067031
INTEGRATED CIRCUIT DEVICES WITH HYBRID METAL LINES Dec 15, 2022 Pending
Array ( [id] => 20431388 [patent_doc_number] => 20250393482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => CONTROLLABLE QUBIT DEVICE WITH A SINGLE JOSEPHSON JUNCTION [patent_app_type] => utility [patent_app_number] => 18/066513 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066513
CONTROLLABLE QUBIT DEVICE WITH A SINGLE JOSEPHSON JUNCTION Dec 14, 2022 Pending
Array ( [id] => 19237486 [patent_doc_number] => 20240194681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => CIRCUIT LAYOUTS WITH VARIABLE CIRCUIT CELL HEIGHTS IN THE SAME CIRCUIT ROW [patent_app_type] => utility [patent_app_number] => 18/079079 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079079
CIRCUIT LAYOUTS WITH VARIABLE CIRCUIT CELL HEIGHTS IN THE SAME CIRCUIT ROW Dec 11, 2022 Pending
Array ( [id] => 19694304 [patent_doc_number] => 20250012849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => ARRANGEMENT AND METHOD FOR TESTING OPTOELECTRONIC COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/710303 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18710303 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/710303
ARRANGEMENT AND METHOD FOR TESTING OPTOELECTRONIC COMPONENTS Nov 16, 2022 Pending
Array ( [id] => 18396947 [patent_doc_number] => 20230165168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SUPERCONDUCTING DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/984363 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17984363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/984363
Superconducting device and method for manufacturing the same Nov 9, 2022 Issued
Array ( [id] => 20532305 [patent_doc_number] => 12550759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 18/053806 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 1258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/053806
Semiconductor package Nov 8, 2022 Issued
Array ( [id] => 18812716 [patent_doc_number] => 20230387053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/983469 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983469
Non-volatile memory device Nov 8, 2022 Issued
Array ( [id] => 18774459 [patent_doc_number] => 20230369290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR CHIP INCLUDING A STRESS CONCENTRATION PORTION [patent_app_type] => utility [patent_app_number] => 17/978846 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17978846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/978846
Method of manufacturing a semiconductor chip including a stress concentration portion Oct 31, 2022 Issued
Array ( [id] => 19328893 [patent_doc_number] => 12046582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Methods of forming microelectronic devices including source structures overlying stack structures [patent_app_type] => utility [patent_app_number] => 18/051459 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051459
Methods of forming microelectronic devices including source structures overlying stack structures Oct 30, 2022 Issued
Array ( [id] => 20669072 [patent_doc_number] => 12610865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Semiconductor device and semiconductor package [patent_app_type] => utility [patent_app_number] => 18/049901 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3266 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049901 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/049901
Semiconductor device and semiconductor package Oct 25, 2022 Issued
Array ( [id] => 18440117 [patent_doc_number] => 20230187412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => POWER DISTRIBUTION FOR STACKED ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/048586 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048586 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/048586
POWER DISTRIBUTION FOR STACKED ELECTRONIC DEVICES Oct 20, 2022 Pending
Array ( [id] => 18311023 [patent_doc_number] => 20230114923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/046121 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046121
Display device Oct 11, 2022 Issued
Array ( [id] => 18349390 [patent_doc_number] => 20230137501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => CURRENT LIMITING DIODE [patent_app_type] => utility [patent_app_number] => 17/957273 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957273
Current limiting diode Sep 29, 2022 Issued
Array ( [id] => 19071251 [patent_doc_number] => 20240105677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE [patent_app_type] => utility [patent_app_number] => 17/955269 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955269 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/955269
RECONSTITUTED WAFER WITH SIDE-STACKED INTEGRATED CIRCUIT DIE Sep 27, 2022 Pending
Array ( [id] => 19524005 [patent_doc_number] => 12125745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Electrical component with a dielectric passivation stack [patent_app_type] => utility [patent_app_number] => 17/949325 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949325
Electrical component with a dielectric passivation stack Sep 20, 2022 Issued
Array ( [id] => 20776992 [patent_doc_number] => 12660691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => High density semiconductor device including integrated controller, logic circuit and memory dies [patent_app_type] => utility [patent_app_number] => 17/949069 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 3451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949069
High density semiconductor device including integrated controller, logic circuit and memory dies Sep 19, 2022 Issued
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