Search

Hung K. Vu

Examiner (ID: 9736)

Most Active Art Unit
2897
Art Unit(s)
2811, 2897
Total Applications
1874
Issued Applications
1571
Pending Applications
97
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17486071 [patent_doc_number] => 20220093575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ACTIVE INTERPOSER [patent_app_type] => utility [patent_app_number] => 17/537972 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537972
Method for fabricating semiconductor device with active interposer Nov 29, 2021 Issued
Array ( [id] => 18394892 [patent_doc_number] => 20230163113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/532754 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532754
Package comprising channel interconnects located between solder interconnects Nov 21, 2021 Issued
Array ( [id] => 18447038 [patent_doc_number] => 11682614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Semiconductor package and package substrate including vent hole [patent_app_type] => utility [patent_app_number] => 17/525388 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4820 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525388
Semiconductor package and package substrate including vent hole Nov 11, 2021 Issued
Array ( [id] => 18563112 [patent_doc_number] => 11728366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Extra doped region for back-side deep trench isolation [patent_app_type] => utility [patent_app_number] => 17/519784 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519784
Extra doped region for back-side deep trench isolation Nov 4, 2021 Issued
Array ( [id] => 18943561 [patent_doc_number] => 20240038700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => DRIVE CHIP AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/613003 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17613003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/613003
Drive chip and display panel Oct 19, 2021 Issued
Array ( [id] => 19015175 [patent_doc_number] => 11922108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Method of forming a memory cell array circuit [patent_app_type] => utility [patent_app_number] => 17/504805 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 21669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504805
Method of forming a memory cell array circuit Oct 18, 2021 Issued
Array ( [id] => 17448347 [patent_doc_number] => 20220068852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD OF FABRICATING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/501133 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501133
Method of fabricating a semiconductor device Oct 13, 2021 Issued
Array ( [id] => 19123583 [patent_doc_number] => 11967577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/498843 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10230 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498843 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498843
Semiconductor device and method for manufacturing the same Oct 11, 2021 Issued
Array ( [id] => 17780215 [patent_doc_number] => 20220246565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => Bump Integration with Redistribution Layer [patent_app_type] => utility [patent_app_number] => 17/492126 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492126
Bump integration with redistribution layer Sep 30, 2021 Issued
Array ( [id] => 18265407 [patent_doc_number] => 20230086649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => Semiconductor Chip Package Having Internal I/O Structures With Modulated Thickness To Compensate For Die/Substrate Warpage [patent_app_type] => utility [patent_app_number] => 17/483621 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483621
Semiconductor Chip Package Having Internal I/O Structures With Modulated Thickness To Compensate For Die/Substrate Warpage Sep 22, 2021 Pending
Array ( [id] => 18008737 [patent_doc_number] => 20220367504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => MEMORY PERIPHERAL CIRCUIT HAVING THREE-DIMENSIONAL TRANSISTORS AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/482026 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482026
Memory peripheral circuit having three-dimensional transistors and method for forming the same Sep 21, 2021 Issued
Array ( [id] => 17486160 [patent_doc_number] => 20220093664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => RELIABLE SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 17/478978 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/478978
Reliable semiconductor packages Sep 19, 2021 Issued
Array ( [id] => 17993446 [patent_doc_number] => 20220359483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/474461 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474461
Semiconductor packages and methods for forming the same Sep 13, 2021 Issued
Array ( [id] => 20276447 [patent_doc_number] => 12446236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Resistive random-access memory using stacked technology [patent_app_type] => utility [patent_app_number] => 18/025971 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 1259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/025971
Resistive random-access memory using stacked technology Sep 12, 2021 Issued
Array ( [id] => 18226744 [patent_doc_number] => 20230065738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DIFFUSION SOLDERING PREFORM WITH VARYING SURFACE PROFILE [patent_app_type] => utility [patent_app_number] => 17/462573 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462573 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462573
Diffusion soldering preform with varying surface profile Aug 30, 2021 Issued
Array ( [id] => 18579124 [patent_doc_number] => 11735664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Source/drain regions of FINFET devices and methods of forming same [patent_app_type] => utility [patent_app_number] => 17/460453 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 8554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460453
Source/drain regions of FINFET devices and methods of forming same Aug 29, 2021 Issued
Array ( [id] => 17339490 [patent_doc_number] => 20220005821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => 3D MEMORY SEMICONDUCTOR DEVICE AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/461075 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461075
3D memory semiconductor device and structure Aug 29, 2021 Issued
Array ( [id] => 19108682 [patent_doc_number] => 11961796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Semiconductor package dielectric substrate including a trench [patent_app_type] => utility [patent_app_number] => 17/461828 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461828
Semiconductor package dielectric substrate including a trench Aug 29, 2021 Issued
Array ( [id] => 18068169 [patent_doc_number] => 20220399257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => INTEGRATED CIRCUIT PACKAGE AND METHOD TO MANUFACTURE THE INTEGRATED CIRCUIT PACKAGE TO REDUCE BOND WIRE DEFECTS IN THE INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 17/460379 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460379
Integrated circuit package and method to manufacture the integrated circuit package to reduce bond wire defects in the integrated circuit package Aug 29, 2021 Issued
Array ( [id] => 17295467 [patent_doc_number] => 20210391306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => METHODS OF FORMING INTEGRATED CIRCUIT PACKAGES [patent_app_type] => utility [patent_app_number] => 17/458549 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458549
Methods of forming integrated circuit packages Aug 26, 2021 Issued
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