Search

Hung T. Nguyen

Examiner (ID: 15433, Phone: (571)272-2982 , Office: P/2682 )

Most Active Art Unit
2612
Art Unit(s)
2681, 2632, 2683, 2612, 2736, 2682, 2636, 2686, 2831
Total Applications
1638
Issued Applications
1316
Pending Applications
51
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8872946 [patent_doc_number] => 08468333 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-18 [patent_title] => 'Updating the system management information of a computer system' [patent_app_type] => utility [patent_app_number] => 12/777025 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12777025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/777025
Updating the system management information of a computer system May 9, 2010 Issued
Array ( [id] => 6475303 [patent_doc_number] => 20100207685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Method and System for Safe and Efficient Chip Power Down Drawing Minimal Current When a Device is not Enabled' [patent_app_type] => utility [patent_app_number] => 12/766701 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5412 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207685.pdf [firstpage_image] =>[orig_patent_app_number] => 12766701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766701
Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled Apr 22, 2010 Issued
Array ( [id] => 6337822 [patent_doc_number] => 20100199120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'STRATEGY TO VERIFY ASYNCHRONOUS LINKS ACROSS CHIPS' [patent_app_type] => utility [patent_app_number] => 12/756998 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7647 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199120.pdf [firstpage_image] =>[orig_patent_app_number] => 12756998 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756998
Strategy to verify asynchronous links across chips Apr 7, 2010 Issued
Array ( [id] => 8060441 [patent_doc_number] => 20110246804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD AND APPARATUS FOR INTERRUPT POWER MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 12/752256 [patent_app_country] => US [patent_app_date] => 2010-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6360 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246804.pdf [firstpage_image] =>[orig_patent_app_number] => 12752256 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/752256
Method and apparatus for interrupt power management Mar 31, 2010 Issued
Array ( [id] => 9500111 [patent_doc_number] => 08738952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Device controller low power mode' [patent_app_type] => utility [patent_app_number] => 12/749203 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4753 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12749203 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749203
Device controller low power mode Mar 28, 2010 Issued
Array ( [id] => 6067555 [patent_doc_number] => 20110202781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'System and Method for Loop Timing Update of Energy Efficient Physical Layer Devices Using Subset Communication Techniques' [patent_app_type] => utility [patent_app_number] => 12/749405 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20110202781.pdf [firstpage_image] =>[orig_patent_app_number] => 12749405 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749405
System and method for loop timing update of energy efficient physical layer devices using subset communication techniques Mar 28, 2010 Issued
Array ( [id] => 6234351 [patent_doc_number] => 20100185886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'INFORMATION PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/726654 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16002 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185886.pdf [firstpage_image] =>[orig_patent_app_number] => 12726654 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726654
Information processing device for assigning interrupts to a first CPU or a second CPU based on a sleeping state Mar 17, 2010 Issued
Array ( [id] => 6020367 [patent_doc_number] => 20110225409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Method and Apparatus for Software Boot Revocation' [patent_app_type] => utility [patent_app_number] => 12/722046 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10461 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225409.pdf [firstpage_image] =>[orig_patent_app_number] => 12722046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722046
Method and apparatus for software boot revocation Mar 10, 2010 Issued
Array ( [id] => 6131242 [patent_doc_number] => 20110087870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'COMPUTING DEVICE WITH DEVELOPER MODE' [patent_app_type] => utility [patent_app_number] => 12/721202 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12454 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20110087870.pdf [firstpage_image] =>[orig_patent_app_number] => 12721202 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721202
Computing device with developer mode Mar 9, 2010 Issued
Array ( [id] => 7658452 [patent_doc_number] => 20110307721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'STORAGE APPARATUS AND POWER CONSUMPTION ESTIMATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/679228 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17116 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307721.pdf [firstpage_image] =>[orig_patent_app_number] => 12679228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/679228
Storage apparatus and power consumption estimation method Mar 4, 2010 Issued
Array ( [id] => 8703817 [patent_doc_number] => 08397053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Multi-motherboard server system' [patent_app_type] => utility [patent_app_number] => 12/699046 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2170 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12699046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699046
Multi-motherboard server system Feb 2, 2010 Issued
Array ( [id] => 6523564 [patent_doc_number] => 20100211767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'COMPUTER SYSTEM, MEMORY CIRCUIT ON MOTHERBOARD AND BOOTING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/699049 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2972 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20100211767.pdf [firstpage_image] =>[orig_patent_app_number] => 12699049 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699049
Booting method using a backup memory in place of a failed main memory Feb 2, 2010 Issued
Array ( [id] => 9242271 [patent_doc_number] => 08607077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Multi-function integrated device and operating method thereof' [patent_app_type] => utility [patent_app_number] => 12/699072 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4795 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12699072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699072
Multi-function integrated device and operating method thereof Feb 2, 2010 Issued
Array ( [id] => 8985160 [patent_doc_number] => 08516290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Clocking scheme for bridge system' [patent_app_type] => utility [patent_app_number] => 12/698752 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5235 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698752
Clocking scheme for bridge system Feb 1, 2010 Issued
Array ( [id] => 8763270 [patent_doc_number] => 08423808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Control device and control system' [patent_app_type] => utility [patent_app_number] => 12/698535 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9199 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698535
Control device and control system Feb 1, 2010 Issued
Array ( [id] => 6337816 [patent_doc_number] => 20100199119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'COMPUTER SYSTEM AND METHOD FOR OVERCLOCKING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/698160 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2871 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199119.pdf [firstpage_image] =>[orig_patent_app_number] => 12698160 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698160
COMPUTER SYSTEM AND METHOD FOR OVERCLOCKING THE SAME Feb 1, 2010 Abandoned
Array ( [id] => 8998155 [patent_doc_number] => 08522060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Computer system, method for controlling the same, and program' [patent_app_type] => utility [patent_app_number] => 12/698578 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8108 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698578
Computer system, method for controlling the same, and program Feb 1, 2010 Issued
Array ( [id] => 6337803 [patent_doc_number] => 20100199113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'APPARATUS AND METHOD FOR MANAGING POWER IN POWER OF ETHERNET SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/698595 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2840 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199113.pdf [firstpage_image] =>[orig_patent_app_number] => 12698595 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698595
Apparatus and method for managing power in power of ethernet system Feb 1, 2010 Issued
Array ( [id] => 9472355 [patent_doc_number] => 08726002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Embedded managed system services repository' [patent_app_type] => utility [patent_app_number] => 12/698297 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3047 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698297 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698297
Embedded managed system services repository Feb 1, 2010 Issued
Array ( [id] => 8741182 [patent_doc_number] => 08412968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Circuit, system and method for selectively turning off internal clock drivers' [patent_app_type] => utility [patent_app_number] => 12/652897 [patent_app_country] => US [patent_app_date] => 2010-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3565 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12652897 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/652897
Circuit, system and method for selectively turning off internal clock drivers Jan 5, 2010 Issued
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