Search

Hung T. Nguyen

Examiner (ID: 15433, Phone: (571)272-2982 , Office: P/2682 )

Most Active Art Unit
2612
Art Unit(s)
2681, 2632, 2683, 2612, 2736, 2682, 2636, 2686, 2831
Total Applications
1638
Issued Applications
1316
Pending Applications
51
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7993165 [patent_doc_number] => 08078890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'System and method for providing memory performance states in a computing system' [patent_app_type] => utility [patent_app_number] => 11/853255 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2948 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078890.pdf [firstpage_image] =>[orig_patent_app_number] => 11853255 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853255
System and method for providing memory performance states in a computing system Sep 10, 2007 Issued
Array ( [id] => 4508240 [patent_doc_number] => 07958344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Method for adjusting set-up default value of bios and mainboard using the same method' [patent_app_type] => utility [patent_app_number] => 11/852512 [patent_app_country] => US [patent_app_date] => 2007-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3573 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958344.pdf [firstpage_image] =>[orig_patent_app_number] => 11852512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/852512
Method for adjusting set-up default value of bios and mainboard using the same method Sep 9, 2007 Issued
Array ( [id] => 4744860 [patent_doc_number] => 20080089462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'TIMER CIRCUIT AND SIGNAL PROCESSING CIRCUIT INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/851201 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6566 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20080089462.pdf [firstpage_image] =>[orig_patent_app_number] => 11851201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851201
TIMER CIRCUIT AND SIGNAL PROCESSING CIRCUIT INCLUDING THE SAME Sep 5, 2007 Abandoned
Array ( [id] => 5231170 [patent_doc_number] => 20070293278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'CIRCUIT AND OPERATING METHOD FOR INTEGRATED INTERFACE OF PDA AND WIRELESS COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/844347 [patent_app_country] => US [patent_app_date] => 2007-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4913 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20070293278.pdf [firstpage_image] =>[orig_patent_app_number] => 11844347 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/844347
Circuit and operating method for integrated interface of PDA and wireless communication system Aug 22, 2007 Issued
Array ( [id] => 7532577 [patent_doc_number] => 07844811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Using chip select to specify boot memory' [patent_app_type] => utility [patent_app_number] => 11/895156 [patent_app_country] => US [patent_app_date] => 2007-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4852 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844811.pdf [firstpage_image] =>[orig_patent_app_number] => 11895156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/895156
Using chip select to specify boot memory Aug 22, 2007 Issued
Array ( [id] => 66512 [patent_doc_number] => 07765414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Circuit and operating method for integrated interface of PDA and wireless communication system' [patent_app_type] => utility [patent_app_number] => 11/844349 [patent_app_country] => US [patent_app_date] => 2007-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5812 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765414.pdf [firstpage_image] =>[orig_patent_app_number] => 11844349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/844349
Circuit and operating method for integrated interface of PDA and wireless communication system Aug 22, 2007 Issued
Array ( [id] => 4581710 [patent_doc_number] => 07840823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Processor system for varying clock frequency and voltage in response to a comparison of instruction execution rate to a reference value' [patent_app_type] => utility [patent_app_number] => 11/892340 [patent_app_country] => US [patent_app_date] => 2007-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3938 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840823.pdf [firstpage_image] =>[orig_patent_app_number] => 11892340 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892340
Processor system for varying clock frequency and voltage in response to a comparison of instruction execution rate to a reference value Aug 21, 2007 Issued
Array ( [id] => 4945460 [patent_doc_number] => 20080082787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Delay circuit and processor' [patent_app_type] => utility [patent_app_number] => 11/892210 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9501 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082787.pdf [firstpage_image] =>[orig_patent_app_number] => 11892210 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892210
Delay circuit and processor Aug 20, 2007 Abandoned
Array ( [id] => 5339213 [patent_doc_number] => 20090055677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Asynchronous first in first out interface and operation method thereof' [patent_app_type] => utility [patent_app_number] => 11/892238 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5308 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055677.pdf [firstpage_image] =>[orig_patent_app_number] => 11892238 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892238
Asynchronous first in first out interface and operation method thereof Aug 20, 2007 Issued
Array ( [id] => 4810700 [patent_doc_number] => 20080191331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'System in package semiconductor device suitable for efficient power management and method of managing power of the same' [patent_app_type] => utility [patent_app_number] => 11/891908 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6225 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191331.pdf [firstpage_image] =>[orig_patent_app_number] => 11891908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/891908
System in package semiconductor device suitable for efficient power management and method of managing power of the same Aug 13, 2007 Issued
Array ( [id] => 4530619 [patent_doc_number] => 07913099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Dynamic processor operating voltage control in response to a change in a core/bus clock frequency ratio' [patent_app_type] => utility [patent_app_number] => 11/890931 [patent_app_country] => US [patent_app_date] => 2007-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1985 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/913/07913099.pdf [firstpage_image] =>[orig_patent_app_number] => 11890931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/890931
Dynamic processor operating voltage control in response to a change in a core/bus clock frequency ratio Aug 7, 2007 Issued
Array ( [id] => 4653343 [patent_doc_number] => 20080040600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'System and Method for Reducing Instability In An Information Handling System' [patent_app_type] => utility [patent_app_number] => 11/834116 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5116 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040600.pdf [firstpage_image] =>[orig_patent_app_number] => 11834116 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/834116
System and method for reducing instability in an information handling system Aug 5, 2007 Issued
Array ( [id] => 4470078 [patent_doc_number] => 07882376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Power control for a core circuit area of a semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/782006 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4369 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882376.pdf [firstpage_image] =>[orig_patent_app_number] => 11782006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782006
Power control for a core circuit area of a semiconductor integrated circuit device Jul 23, 2007 Issued
Array ( [id] => 5523166 [patent_doc_number] => 20090031147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'APPARATUS FOR WAKING UP A DEVICE' [patent_app_type] => utility [patent_app_number] => 11/782100 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2520 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031147.pdf [firstpage_image] =>[orig_patent_app_number] => 11782100 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782100
APPARATUS FOR WAKING UP A DEVICE Jul 23, 2007 Abandoned
Array ( [id] => 4881912 [patent_doc_number] => 20080155295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'SYNCHRONIZATION CONTROL APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/782053 [patent_app_country] => US [patent_app_date] => 2007-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7694 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155295.pdf [firstpage_image] =>[orig_patent_app_number] => 11782053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782053
SYNCHRONIZATION CONTROL APPARATUS Jul 23, 2007 Abandoned
Array ( [id] => 5012706 [patent_doc_number] => 20070283185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY' [patent_app_type] => utility [patent_app_number] => 11/772418 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4620 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283185.pdf [firstpage_image] =>[orig_patent_app_number] => 11772418 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772418
Digital reliability monitor having autonomic repair and notification capability Jul 1, 2007 Issued
Array ( [id] => 321392 [patent_doc_number] => 07523329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Apparatus for and method of reducing power consumption in a cable modem' [patent_app_type] => utility [patent_app_number] => 11/764914 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6486 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523329.pdf [firstpage_image] =>[orig_patent_app_number] => 11764914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764914
Apparatus for and method of reducing power consumption in a cable modem Jun 18, 2007 Issued
Array ( [id] => 157882 [patent_doc_number] => 07685442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Method and systems for a radiation tolerant bus interface circuit' [patent_app_type] => utility [patent_app_number] => 11/740386 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9611 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685442.pdf [firstpage_image] =>[orig_patent_app_number] => 11740386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740386
Method and systems for a radiation tolerant bus interface circuit Apr 25, 2007 Issued
Array ( [id] => 4592070 [patent_doc_number] => 07836324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Oversampling-based scheme for synchronous interface communication' [patent_app_type] => utility [patent_app_number] => 11/740452 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6652 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836324.pdf [firstpage_image] =>[orig_patent_app_number] => 11740452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740452
Oversampling-based scheme for synchronous interface communication Apr 25, 2007 Issued
Array ( [id] => 4862303 [patent_doc_number] => 20080270811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory' [patent_app_type] => utility [patent_app_number] => 11/740398 [patent_app_country] => US [patent_app_date] => 2007-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270811.pdf [firstpage_image] =>[orig_patent_app_number] => 11740398 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740398
Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory Apr 25, 2007 Abandoned
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