Search

Hung T. Nguyen

Examiner (ID: 15433, Phone: (571)272-2982 , Office: P/2682 )

Most Active Art Unit
2612
Art Unit(s)
2681, 2632, 2683, 2612, 2736, 2682, 2636, 2686, 2831
Total Applications
1638
Issued Applications
1316
Pending Applications
51
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4862318 [patent_doc_number] => 20080270816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Portable data storage apparatus and synchronization method for the same' [patent_app_type] => utility [patent_app_number] => 11/790318 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3285 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270816.pdf [firstpage_image] =>[orig_patent_app_number] => 11790318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790318
Portable data storage apparatus and synchronization method for the same Apr 24, 2007 Abandoned
Array ( [id] => 4895333 [patent_doc_number] => 20080104433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'System on a chip with RTC power supply' [patent_app_type] => utility [patent_app_number] => 11/789763 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4144 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104433.pdf [firstpage_image] =>[orig_patent_app_number] => 11789763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/789763
System on a chip with RTC power supply Apr 24, 2007 Issued
Array ( [id] => 4895334 [patent_doc_number] => 20080104434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'SOC with low power and performance modes' [patent_app_type] => utility [patent_app_number] => 11/789760 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4019 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104434.pdf [firstpage_image] =>[orig_patent_app_number] => 11789760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/789760
SOC with low power and performance modes Apr 24, 2007 Issued
Array ( [id] => 9254 [patent_doc_number] => 07814356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Apparatus and control method for initializing a phase adjusting part in response to a power supply cut signal' [patent_app_type] => utility [patent_app_number] => 11/790260 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5917 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/814/07814356.pdf [firstpage_image] =>[orig_patent_app_number] => 11790260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790260
Apparatus and control method for initializing a phase adjusting part in response to a power supply cut signal Apr 23, 2007 Issued
Array ( [id] => 68978 [patent_doc_number] => 07761721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'System of integrated environmentally hardened architecture for space application' [patent_app_type] => utility [patent_app_number] => 11/734482 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761721.pdf [firstpage_image] =>[orig_patent_app_number] => 11734482 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/734482
System of integrated environmentally hardened architecture for space application Apr 11, 2007 Issued
Array ( [id] => 4665475 [patent_doc_number] => 20080256382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'METHOD AND SYSTEM FOR DIGITAL FREQUENCY CLOCKING IN PROCESSOR CORES' [patent_app_type] => utility [patent_app_number] => 11/734375 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3845 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256382.pdf [firstpage_image] =>[orig_patent_app_number] => 11734375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/734375
Method and system for digital frequency clocking in processor cores Apr 11, 2007 Issued
Array ( [id] => 9250 [patent_doc_number] => 07814352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Selective connection of a memory to either a gateway card or information processor based on the power mode' [patent_app_type] => utility [patent_app_number] => 11/783786 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/814/07814352.pdf [firstpage_image] =>[orig_patent_app_number] => 11783786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783786
Selective connection of a memory to either a gateway card or information processor based on the power mode Apr 11, 2007 Issued
Array ( [id] => 8120183 [patent_doc_number] => 08161314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Method and system for analog frequency clocking in processor cores' [patent_app_type] => utility [patent_app_number] => 11/734334 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161314.pdf [firstpage_image] =>[orig_patent_app_number] => 11734334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/734334
Method and system for analog frequency clocking in processor cores Apr 11, 2007 Issued
Array ( [id] => 4522371 [patent_doc_number] => 07917741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Enhancing security of a system via access by an embedded controller to a secure storage device' [patent_app_type] => utility [patent_app_number] => 11/733599 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5388 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917741.pdf [firstpage_image] =>[orig_patent_app_number] => 11733599 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733599
Enhancing security of a system via access by an embedded controller to a secure storage device Apr 9, 2007 Issued
Array ( [id] => 4470068 [patent_doc_number] => 07882372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Method and system for controlling and monitoring an array of point-of-load regulators' [patent_app_type] => utility [patent_app_number] => 11/696449 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4050 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882372.pdf [firstpage_image] =>[orig_patent_app_number] => 11696449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/696449
Method and system for controlling and monitoring an array of point-of-load regulators Apr 3, 2007 Issued
Array ( [id] => 5223859 [patent_doc_number] => 20070253125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/730683 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8942 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253125.pdf [firstpage_image] =>[orig_patent_app_number] => 11730683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730683
Power control for a plurality of internal power supply circuits of a semiconductor integrated circuit Apr 2, 2007 Issued
Array ( [id] => 5167133 [patent_doc_number] => 20070288722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Information processing device' [patent_app_type] => utility [patent_app_number] => 11/730198 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2991 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288722.pdf [firstpage_image] =>[orig_patent_app_number] => 11730198 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730198
Information processing device Mar 28, 2007 Abandoned
Array ( [id] => 4722408 [patent_doc_number] => 20080244255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Method for not resetting memory while booting computer through hardware booting button thereof' [patent_app_type] => utility [patent_app_number] => 11/730022 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1397 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244255.pdf [firstpage_image] =>[orig_patent_app_number] => 11730022 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730022
Method for not resetting memory while booting computer through hardware booting button thereof Mar 28, 2007 Abandoned
Array ( [id] => 58524 [patent_doc_number] => 07769990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-03 [patent_title] => 'Using a monitoring process to update system configuration settings during restore operations' [patent_app_type] => utility [patent_app_number] => 11/690653 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 24825 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/769/07769990.pdf [firstpage_image] =>[orig_patent_app_number] => 11690653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/690653
Using a monitoring process to update system configuration settings during restore operations Mar 22, 2007 Issued
Array ( [id] => 4730580 [patent_doc_number] => 20080209233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'TECHNIQUES FOR OPERATING A PROCESSOR SUBSYSTEM' [patent_app_type] => utility [patent_app_number] => 11/678440 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3161 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209233.pdf [firstpage_image] =>[orig_patent_app_number] => 11678440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678440
Techniques for operating a processor subsystem to service masked interrupts during a power-down sequence Feb 22, 2007 Issued
Array ( [id] => 4874853 [patent_doc_number] => 20080201587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'ANTICIPATORY POWER MANAGEMENT FOR BATTERY-POWERED ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/675979 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6899 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201587.pdf [firstpage_image] =>[orig_patent_app_number] => 11675979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675979
Anticipatory power management for battery-powered electronic device Feb 15, 2007 Issued
Array ( [id] => 5260781 [patent_doc_number] => 20070214414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Method for reducing booting time of mobile communication terminal' [patent_app_type] => utility [patent_app_number] => 11/706877 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2979 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214414.pdf [firstpage_image] =>[orig_patent_app_number] => 11706877 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706877
Method for reducing booting time of mobile communication terminal Feb 14, 2007 Issued
Array ( [id] => 4787687 [patent_doc_number] => 20080141016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Computer System and Related Method for Preventing Failure of Updating BIOS Programs' [patent_app_type] => utility [patent_app_number] => 11/675088 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5416 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141016.pdf [firstpage_image] =>[orig_patent_app_number] => 11675088 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675088
Computer System and Related Method for Preventing Failure of Updating BIOS Programs Feb 14, 2007 Abandoned
Array ( [id] => 4869022 [patent_doc_number] => 20080148081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'System and method for controlling power delivered to a powered device based on cable characteristics' [patent_app_type] => utility [patent_app_number] => 11/654023 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6845 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148081.pdf [firstpage_image] =>[orig_patent_app_number] => 11654023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654023
System and method for controlling power delivered to a powered device based on cable characteristics Jan 16, 2007 Issued
Array ( [id] => 898175 [patent_doc_number] => 07346798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Circuit and method for aligning transmitted data by adjusting transmission timing for plurality of lanes' [patent_app_type] => utility [patent_app_number] => 11/624201 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6783 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346798.pdf [firstpage_image] =>[orig_patent_app_number] => 11624201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/624201
Circuit and method for aligning transmitted data by adjusting transmission timing for plurality of lanes Jan 16, 2007 Issued
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