
Hung T. Nguyen
Examiner (ID: 15433, Phone: (571)272-2982 , Office: P/2682 )
| Most Active Art Unit | 2612 |
| Art Unit(s) | 2681, 2632, 2683, 2612, 2736, 2682, 2636, 2686, 2831 |
| Total Applications | 1638 |
| Issued Applications | 1316 |
| Pending Applications | 51 |
| Abandoned Applications | 276 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7021735
[patent_doc_number] => 20050223249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-06
[patent_title] => 'Managing power consumption by requesting an adjustment to an operating point of a processor'
[patent_app_type] => utility
[patent_app_number] => 10/814425
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4409
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20050223249.pdf
[firstpage_image] =>[orig_patent_app_number] => 10814425
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/814425 | Managing power consumption by requesting an adjustment to an operating point of a processor | Mar 29, 2004 | Issued |
Array
(
[id] => 7196572
[patent_doc_number] => 20040205366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Method for avoiding data loss in a PDA'
[patent_app_type] => new
[patent_app_number] => 10/812082
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2105
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20040205366.pdf
[firstpage_image] =>[orig_patent_app_number] => 10812082
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/812082 | Method for avoiding data loss in a PDA | Mar 29, 2004 | Abandoned |
Array
(
[id] => 6992510
[patent_doc_number] => 20050091547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'High speed non-volatile electronic memory configuration'
[patent_app_type] => utility
[patent_app_number] => 10/811913
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4137
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20050091547.pdf
[firstpage_image] =>[orig_patent_app_number] => 10811913
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/811913 | High speed non-volatile electronic memory configuration | Mar 29, 2004 | Issued |
Array
(
[id] => 7021731
[patent_doc_number] => 20050223245
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-06
[patent_title] => 'Enabling and disabling of powering-off of computer system'
[patent_app_type] => utility
[patent_app_number] => 10/812486
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4499
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20050223245.pdf
[firstpage_image] =>[orig_patent_app_number] => 10812486
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/812486 | Enabling and disabling of powering-off of computer system | Mar 29, 2004 | Issued |
Array
(
[id] => 481517
[patent_doc_number] => 07228442
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Method and systems for a radiation tolerant bus interface circuit'
[patent_app_type] => utility
[patent_app_number] => 10/813152
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9568
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/228/07228442.pdf
[firstpage_image] =>[orig_patent_app_number] => 10813152
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/813152 | Method and systems for a radiation tolerant bus interface circuit | Mar 29, 2004 | Issued |
Array
(
[id] => 7262372
[patent_doc_number] => 20050144488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Method and apparatus of lowering I/O bus power consumption'
[patent_app_type] => utility
[patent_app_number] => 10/810119
[patent_app_country] => US
[patent_app_date] => 2004-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3324
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20050144488.pdf
[firstpage_image] =>[orig_patent_app_number] => 10810119
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/810119 | Method and apparatus of lowering I/O bus power consumption | Mar 24, 2004 | Abandoned |
Array
(
[id] => 593614
[patent_doc_number] => 07461244
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-02
[patent_title] => 'Method and apparatus to support booting despite deficient resources'
[patent_app_type] => utility
[patent_app_number] => 10/587448
[patent_app_country] => US
[patent_app_date] => 2004-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3554
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/461/07461244.pdf
[firstpage_image] =>[orig_patent_app_number] => 10587448
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/587448 | Method and apparatus to support booting despite deficient resources | Mar 17, 2004 | Issued |
Array
(
[id] => 7109185
[patent_doc_number] => 20050206639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Safety and protective personal computer power supply display device'
[patent_app_type] => utility
[patent_app_number] => 10/801666
[patent_app_country] => US
[patent_app_date] => 2004-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1425
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0206/20050206639.pdf
[firstpage_image] =>[orig_patent_app_number] => 10801666
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/801666 | Safety and protective personal computer power supply display device | Mar 16, 2004 | Abandoned |
Array
(
[id] => 241399
[patent_doc_number] => 07594125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-22
[patent_title] => 'Power management in an IEEE 802.11 IBSS using an end of ATIM frame and a dynamically determined ATIM period'
[patent_app_type] => utility
[patent_app_number] => 10/547092
[patent_app_country] => US
[patent_app_date] => 2004-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4098
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/594/07594125.pdf
[firstpage_image] =>[orig_patent_app_number] => 10547092
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/547092 | Power management in an IEEE 802.11 IBSS using an end of ATIM frame and a dynamically determined ATIM period | Feb 22, 2004 | Issued |
Array
(
[id] => 7247055
[patent_doc_number] => 20040158756
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Low power processor'
[patent_app_type] => new
[patent_app_number] => 10/768136
[patent_app_country] => US
[patent_app_date] => 2004-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12244
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 21
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20040158756.pdf
[firstpage_image] =>[orig_patent_app_number] => 10768136
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/768136 | Substrate bias switching unit for a low power processor | Feb 1, 2004 | Issued |
Array
(
[id] => 7037491
[patent_doc_number] => 20050156925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Graphical user interface for pre-boot operating environment'
[patent_app_type] => utility
[patent_app_number] => 10/758847
[patent_app_country] => US
[patent_app_date] => 2004-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3002
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20050156925.pdf
[firstpage_image] =>[orig_patent_app_number] => 10758847
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/758847 | Graphical user interface for pre-boot operating environment | Jan 15, 2004 | Abandoned |
Array
(
[id] => 5597879
[patent_doc_number] => 20060161797
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Asynchronous wrapper for a globally asynchronous, locally synchronous (gals) circuit'
[patent_app_type] => utility
[patent_app_number] => 10/542938
[patent_app_country] => US
[patent_app_date] => 2003-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7520
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20060161797.pdf
[firstpage_image] =>[orig_patent_app_number] => 10542938
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/542938 | Asynchronous wrapper for a globally asynchronous, locally synchronous (GALS) circuit | Dec 28, 2003 | Issued |
Array
(
[id] => 7437223
[patent_doc_number] => 20040230855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'Method and/or apparatus for paging to a dynamic memory array'
[patent_app_type] => new
[patent_app_number] => 10/733751
[patent_app_country] => US
[patent_app_date] => 2003-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5993
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20040230855.pdf
[firstpage_image] =>[orig_patent_app_number] => 10733751
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/733751 | Method and/or apparatus for paging to a dynamic memory array | Dec 10, 2003 | Issued |
Array
(
[id] => 7300561
[patent_doc_number] => 20040215989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Information processor, program, storage medium, and control method'
[patent_app_type] => new
[patent_app_number] => 10/731903
[patent_app_country] => US
[patent_app_date] => 2003-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4843
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20040215989.pdf
[firstpage_image] =>[orig_patent_app_number] => 10731903
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/731903 | Information processor, program, storage medium, and control method | Dec 9, 2003 | Issued |
Array
(
[id] => 513383
[patent_doc_number] => 07206948
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'System and method for reducing power usage'
[patent_app_type] => utility
[patent_app_number] => 10/731283
[patent_app_country] => US
[patent_app_date] => 2003-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7102
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/206/07206948.pdf
[firstpage_image] =>[orig_patent_app_number] => 10731283
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/731283 | System and method for reducing power usage | Dec 8, 2003 | Issued |
Array
(
[id] => 451229
[patent_doc_number] => 07254727
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Information processor with suppressed cache coherence in low power mode'
[patent_app_type] => utility
[patent_app_number] => 10/730672
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4687
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/254/07254727.pdf
[firstpage_image] =>[orig_patent_app_number] => 10730672
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/730672 | Information processor with suppressed cache coherence in low power mode | Dec 7, 2003 | Issued |
Array
(
[id] => 7185243
[patent_doc_number] => 20050125586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Alternate non-volatile memory for robust I/O'
[patent_app_type] => utility
[patent_app_number] => 10/730154
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1946
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20050125586.pdf
[firstpage_image] =>[orig_patent_app_number] => 10730154
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/730154 | Alternate non-volatile memory for robust I/O | Dec 7, 2003 | Issued |
Array
(
[id] => 823450
[patent_doc_number] => 07409572
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-08-05
[patent_title] => 'Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board'
[patent_app_type] => utility
[patent_app_number] => 10/728492
[patent_app_country] => US
[patent_app_date] => 2003-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 6713
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/409/07409572.pdf
[firstpage_image] =>[orig_patent_app_number] => 10728492
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728492 | Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board | Dec 4, 2003 | Issued |
Array
(
[id] => 7185895
[patent_doc_number] => 20050125707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Digital reliability monitor having autonomic repair and notification capability'
[patent_app_type] => utility
[patent_app_number] => 10/729751
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4599
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20050125707.pdf
[firstpage_image] =>[orig_patent_app_number] => 10729751
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/729751 | Digital reliability monitor having autonomic repair and notification capability | Dec 3, 2003 | Issued |
Array
(
[id] => 5879197
[patent_doc_number] => 20060168463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Register file gating to reduce microprocessor power dissipation'
[patent_app_type] => utility
[patent_app_number] => 10/561627
[patent_app_country] => US
[patent_app_date] => 2003-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7425
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20060168463.pdf
[firstpage_image] =>[orig_patent_app_number] => 10561627
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/561627 | Register file gating to reduce microprocessor power dissipation | Dec 2, 2003 | Issued |