Search

Hung T. Nguyen

Examiner (ID: 15433, Phone: (571)272-2982 , Office: P/2682 )

Most Active Art Unit
2612
Art Unit(s)
2681, 2632, 2683, 2612, 2736, 2682, 2636, 2686, 2831
Total Applications
1638
Issued Applications
1316
Pending Applications
51
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6752079 [patent_doc_number] => 20030046600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Processor' [patent_app_type] => new [patent_app_number] => 10/234857 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11445 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046600.pdf [firstpage_image] =>[orig_patent_app_number] => 10234857 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/234857
Processor capable of preventing sleep/hold state based on a difference between a processing block address and a writing block address Sep 4, 2002 Issued
Array ( [id] => 7367921 [patent_doc_number] => 20040015734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Automatic output delay timing adjustment for programmable glitch filter' [patent_app_type] => new [patent_app_number] => 10/199261 [patent_app_country] => US [patent_app_date] => 2002-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7526 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015734.pdf [firstpage_image] =>[orig_patent_app_number] => 10199261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/199261
Automatic output delay timing adjustment for programmable glitch filter Jul 18, 2002 Issued
Array ( [id] => 619782 [patent_doc_number] => 07146510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-05 [patent_title] => 'Use of a signal line to adjust width and/or frequency of a communication link during system operation' [patent_app_type] => utility [patent_app_number] => 10/198637 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 14123 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146510.pdf [firstpage_image] =>[orig_patent_app_number] => 10198637 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/198637
Use of a signal line to adjust width and/or frequency of a communication link during system operation Jul 17, 2002 Issued
Array ( [id] => 749519 [patent_doc_number] => 07032120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method and apparatus for minimizing power requirements in a computer peripheral device while in suspend state and returning to full operation state without loss of data' [patent_app_type] => utility [patent_app_number] => 10/197719 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3388 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032120.pdf [firstpage_image] =>[orig_patent_app_number] => 10197719 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197719
Method and apparatus for minimizing power requirements in a computer peripheral device while in suspend state and returning to full operation state without loss of data Jul 17, 2002 Issued
Array ( [id] => 995944 [patent_doc_number] => 06918049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Method and apparatus for controlling the phase of the clock output of a digital clock' [patent_app_type] => utility [patent_app_number] => 10/199260 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/918/06918049.pdf [firstpage_image] =>[orig_patent_app_number] => 10199260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/199260
Method and apparatus for controlling the phase of the clock output of a digital clock Jul 17, 2002 Issued
Array ( [id] => 6693844 [patent_doc_number] => 20030041276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Semiconductor device allowing control of clock supply to processor on a clock cycle basis' [patent_app_type] => new [patent_app_number] => 10/197578 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7290 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20030041276.pdf [firstpage_image] =>[orig_patent_app_number] => 10197578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197578
Semiconductor device allowing control of clock supply to processor on a clock cycle basis Jul 17, 2002 Abandoned
Array ( [id] => 7621138 [patent_doc_number] => 06978363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'System and method to enable a legacy BIOS system to boot from a disk that includes EFI GPT partitions' [patent_app_type] => utility [patent_app_number] => 10/186689 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978363.pdf [firstpage_image] =>[orig_patent_app_number] => 10186689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186689
System and method to enable a legacy BIOS system to boot from a disk that includes EFI GPT partitions Jul 1, 2002 Issued
Array ( [id] => 7446413 [patent_doc_number] => 20040003303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Methods and apparatus for power management' [patent_app_type] => new [patent_app_number] => 10/188271 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5033 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003303.pdf [firstpage_image] =>[orig_patent_app_number] => 10188271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/188271
Methods and apparatus for static and dynamic power management of computer systems Jun 30, 2002 Issued
Array ( [id] => 955179 [patent_doc_number] => 06959395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Method and apparatus for the conditional enablement of PCI power management' [patent_app_type] => utility [patent_app_number] => 10/180148 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2840 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/959/06959395.pdf [firstpage_image] =>[orig_patent_app_number] => 10180148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180148
Method and apparatus for the conditional enablement of PCI power management Jun 25, 2002 Issued
Array ( [id] => 6824481 [patent_doc_number] => 20030235103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Circuit, system and method for selectively turning off internal clock drivers' [patent_app_type] => new [patent_app_number] => 10/179882 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3433 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235103.pdf [firstpage_image] =>[orig_patent_app_number] => 10179882 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179882
Circuit, system and method for selectively turning off internal clock drivers Jun 24, 2002 Issued
Array ( [id] => 609598 [patent_doc_number] => 07155630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Method and unit for selectively enabling an input buffer based on an indication of a clock transition' [patent_app_type] => utility [patent_app_number] => 10/179445 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5278 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155630.pdf [firstpage_image] =>[orig_patent_app_number] => 10179445 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179445
Method and unit for selectively enabling an input buffer based on an indication of a clock transition Jun 24, 2002 Issued
Array ( [id] => 945855 [patent_doc_number] => 06968465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Multiple server in-rush current reduction' [patent_app_type] => utility [patent_app_number] => 10/178300 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4932 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968465.pdf [firstpage_image] =>[orig_patent_app_number] => 10178300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/178300
Multiple server in-rush current reduction Jun 23, 2002 Issued
Array ( [id] => 7608064 [patent_doc_number] => 07000136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Efficient variably-channelized SONET multiplexer and payload mapper' [patent_app_type] => utility [patent_app_number] => 10/176230 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6817 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000136.pdf [firstpage_image] =>[orig_patent_app_number] => 10176230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/176230
Efficient variably-channelized SONET multiplexer and payload mapper Jun 20, 2002 Issued
Array ( [id] => 933461 [patent_doc_number] => 06981167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Programmable controller with sub-phase clocking scheme' [patent_app_type] => utility [patent_app_number] => 10/171449 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981167.pdf [firstpage_image] =>[orig_patent_app_number] => 10171449 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/171449
Programmable controller with sub-phase clocking scheme Jun 12, 2002 Issued
Array ( [id] => 5791613 [patent_doc_number] => 20020162036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Electric power controlling method through a serial bus' [patent_app_type] => new [patent_app_number] => 10/128331 [patent_app_country] => US [patent_app_date] => 2002-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20020162036.pdf [firstpage_image] =>[orig_patent_app_number] => 10128331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/128331
Electric power controlling method through a serial bus Apr 23, 2002 Issued
Array ( [id] => 933392 [patent_doc_number] => 06981134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method and system for processing using a CPU and digital signal processor' [patent_app_type] => utility [patent_app_number] => 10/128366 [patent_app_country] => US [patent_app_date] => 2002-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 61 [patent_no_of_words] => 17259 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981134.pdf [firstpage_image] =>[orig_patent_app_number] => 10128366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/128366
Method and system for processing using a CPU and digital signal processor Apr 23, 2002 Issued
Array ( [id] => 945868 [patent_doc_number] => 06968472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Serial data interface' [patent_app_type] => utility [patent_app_number] => 10/127185 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 10970 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968472.pdf [firstpage_image] =>[orig_patent_app_number] => 10127185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127185
Serial data interface Apr 21, 2002 Issued
Array ( [id] => 513450 [patent_doc_number] => 07206957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Clock distribution circuit' [patent_app_type] => utility [patent_app_number] => 10/127297 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6831 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206957.pdf [firstpage_image] =>[orig_patent_app_number] => 10127297 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/127297
Clock distribution circuit Apr 21, 2002 Issued
Array ( [id] => 6109186 [patent_doc_number] => 20020172097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Methods and apparatus for low power delay control' [patent_app_type] => new [patent_app_number] => 10/126455 [patent_app_country] => US [patent_app_date] => 2002-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20020172097.pdf [firstpage_image] =>[orig_patent_app_number] => 10126455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/126455
Methods and apparatus for low power delay control Apr 18, 2002 Issued
Array ( [id] => 960043 [patent_doc_number] => 06954852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'System for and method of network booting of an operating system to a client computer using hibernation' [patent_app_type] => utility [patent_app_number] => 10/125265 [patent_app_country] => US [patent_app_date] => 2002-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7731 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 454 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954852.pdf [firstpage_image] =>[orig_patent_app_number] => 10125265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/125265
System for and method of network booting of an operating system to a client computer using hibernation Apr 17, 2002 Issued
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