Search

Hwei-siu C Payer

Examiner (ID: 15838, Phone: (571)272-4511 , Office: P/3724 )

Most Active Art Unit
3724
Art Unit(s)
3204, 3724, 2899
Total Applications
3744
Issued Applications
2918
Pending Applications
185
Abandoned Applications
670

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20305883 [patent_doc_number] => 12451887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Dynamic latch, semiconductor chip, computing power board and computing device [patent_app_type] => utility [patent_app_number] => 18/621934 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621934 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621934
Dynamic latch, semiconductor chip, computing power board and computing device Mar 28, 2024 Issued
Array ( [id] => 19681065 [patent_doc_number] => 12192951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Synchronization of receiver and transmitter local oscillators for ranging applications [patent_app_type] => utility [patent_app_number] => 18/618458 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618458
Synchronization of receiver and transmitter local oscillators for ranging applications Mar 26, 2024 Issued
Array ( [id] => 20132751 [patent_doc_number] => 12375069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Method for forming a timing circuit arrangements for flip-flops [patent_app_type] => utility [patent_app_number] => 18/615361 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 8601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615361 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615361
Method for forming a timing circuit arrangements for flip-flops Mar 24, 2024 Issued
Array ( [id] => 19671433 [patent_doc_number] => 12184210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-31 [patent_title] => Fan and lamp control circuit, fan and lamp device, and fan and lamp system [patent_app_type] => utility [patent_app_number] => 18/613722 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7427 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613722 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/613722
Fan and lamp control circuit, fan and lamp device, and fan and lamp system Mar 21, 2024 Issued
Array ( [id] => 20182878 [patent_doc_number] => 20250266836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => BI-DIRECTIONAL LEVEL SHIFTER [patent_app_type] => utility [patent_app_number] => 18/581518 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581518 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581518
BI-DIRECTIONAL LEVEL SHIFTER Feb 19, 2024 Pending
Array ( [id] => 19393587 [patent_doc_number] => 20240283457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => CIRCUITRY AND A METHOD FOR GENERATING A SET OF OUTPUT CLOCK SIGNALS [patent_app_type] => utility [patent_app_number] => 18/444835 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444835 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444835
CIRCUITRY AND A METHOD FOR GENERATING A SET OF OUTPUT CLOCK SIGNALS Feb 18, 2024 Pending
Array ( [id] => 20182877 [patent_doc_number] => 20250266835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => AGING RESILIENT LEVEL SHIFTER [patent_app_type] => utility [patent_app_number] => 18/442632 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442632
AGING RESILIENT LEVEL SHIFTER Feb 14, 2024 Pending
Array ( [id] => 20168355 [patent_doc_number] => 20250260402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => BINARY INVERTER CIRCUITS WITH CONFIGURABLE THRESHOLD VOLTAGES [patent_app_type] => utility [patent_app_number] => 18/440796 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440796 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440796
BINARY INVERTER CIRCUITS WITH CONFIGURABLE THRESHOLD VOLTAGES Feb 12, 2024 Pending
Array ( [id] => 20003223 [patent_doc_number] => 20250141445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => ASYMMETRIC OUTPUT DRIVER [patent_app_type] => utility [patent_app_number] => 18/435329 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435329 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435329
ASYMMETRIC OUTPUT DRIVER Feb 6, 2024 Pending
Array ( [id] => 19350050 [patent_doc_number] => 20240259014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Accurate Reduced Gate-Drive Current Limiter [patent_app_type] => utility [patent_app_number] => 18/435509 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435509
Accurate reduced gate-drive current limiter Feb 6, 2024 Issued
Array ( [id] => 20154007 [patent_doc_number] => 20250253845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => HIGH SPEED HIGH SWING DRIVER FOR DIRECT DRIVE PHOTONIC MODULATORS [patent_app_type] => utility [patent_app_number] => 18/434092 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434092 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434092
High speed high swing driver for direct drive photonic modulators Feb 5, 2024 Issued
Array ( [id] => 20153996 [patent_doc_number] => 20250253834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => Single Phase Clock Controlled Master Latch in Flip Flops [patent_app_type] => utility [patent_app_number] => 18/432199 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432199
Single Phase Clock Controlled Master Latch in Flip Flops Feb 4, 2024 Pending
Array ( [id] => 19836390 [patent_doc_number] => 20250088176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SIGNAL DRIVER CIRCUIT, AND A SEMICONDUCTOR APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/429768 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429768
Signal driver circuit, and a semiconductor apparatus using the same Jan 31, 2024 Issued
Array ( [id] => 19713416 [patent_doc_number] => 20250023558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => METHODS AND APPARATUS TO CONFIGURE A DEVICE USING TIMING [patent_app_type] => utility [patent_app_number] => 18/428966 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428966
METHODS AND APPARATUS TO CONFIGURE A DEVICE USING TIMING Jan 30, 2024 Pending
Array ( [id] => 19238200 [patent_doc_number] => 20240195395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => CIRCUIT AND METHOD FOR COMPENSATING NON-LINEARITIES [patent_app_type] => utility [patent_app_number] => 18/424056 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424056
CIRCUIT AND METHOD FOR COMPENSATING NON-LINEARITIES Jan 25, 2024 Pending
Array ( [id] => 19147246 [patent_doc_number] => 20240146301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => GATE RESISTOR BYPASS FOR RF FET SWITCH STACK [patent_app_type] => utility [patent_app_number] => 18/409152 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409152
GATE RESISTOR BYPASS FOR RF FET SWITCH STACK Jan 9, 2024 Pending
Array ( [id] => 19731927 [patent_doc_number] => 12209919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-28 [patent_title] => Method for implementing Vptat multiplier in high accuracy thermal sensor [patent_app_type] => utility [patent_app_number] => 18/406551 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6952 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406551
Method for implementing Vptat multiplier in high accuracy thermal sensor Jan 7, 2024 Issued
Array ( [id] => 19117219 [patent_doc_number] => 20240128969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => POWER-ON RESET CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/396131 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/396131
Power-on reset circuit Dec 25, 2023 Issued
Array ( [id] => 20244683 [patent_doc_number] => 12425017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Power-on reset circuitry, an implant device and a method for generating a power-on reset signal [patent_app_type] => utility [patent_app_number] => 18/521237 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2487 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521237 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521237
Power-on reset circuitry, an implant device and a method for generating a power-on reset signal Nov 27, 2023 Issued
Array ( [id] => 19935620 [patent_doc_number] => 12308830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Post-driver with low voltage operation and electrostatic discharge protection [patent_app_type] => utility [patent_app_number] => 18/517024 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18517024 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/517024
Post-driver with low voltage operation and electrostatic discharge protection Nov 21, 2023 Issued
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