Hyun D Park

Array ( [id] => 16845743 [patent_doc_number] => 11017837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 16/812944 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13787 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17437066 [patent_doc_number] => 11262391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-01 [patent_title] => Power outage detection [patent_app_type] => utility [patent_app_number] => 16/811110 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16315830 [patent_doc_number] => 20200294568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => MAGNETIC MEMORY AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/806245 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17239344 [patent_doc_number] => 11183232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Output buffer circuit with metal option [patent_app_type] => utility [patent_app_number] => 16/800899 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4073 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16987806 [patent_doc_number] => 11074985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-27 [patent_title] => One-time programmable memory device and method for operating the same [patent_app_type] => utility [patent_app_number] => 16/801121 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5693 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16973434 [patent_doc_number] => 11069413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Memory system and nonvolatile memory [patent_app_type] => utility [patent_app_number] => 16/799885 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 40 [patent_no_of_words] => 21913 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17055554 [patent_doc_number] => 20210264988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => CHARGE LOSS COMPENSATION [patent_app_type] => utility [patent_app_number] => 16/800678 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16879208 [patent_doc_number] => 11029346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Monitoring load operation [patent_app_type] => utility [patent_app_number] => 16/795741 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6782 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16255436 [patent_doc_number] => 20200264810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => HIGH DENSITY FRACTIONAL BIT SOLID STATE DRIVES USING CODED SET PARTITIONS [patent_app_type] => utility [patent_app_number] => 16/796296 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17379812 [patent_doc_number] => 11237828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Secure matrix space with partitions for concurrent use [patent_app_type] => utility [patent_app_number] => 16/783125 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12209 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17092671 [patent_doc_number] => 11120865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Apparatuses and methods for implementing access line loads for sense amplifiers for open access line sensing [patent_app_type] => utility [patent_app_number] => 16/746778 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4438 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17283915 [patent_doc_number] => 11200955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Non-volatile memory device and memory system including the same and program method thereof [patent_app_type] => utility [patent_app_number] => 16/734799 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17359618 [patent_doc_number] => 20220020414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => PAGE POLICIES FOR SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/414823 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17414823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16911447 [patent_doc_number] => 11043497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-22 [patent_title] => Integrated memory having non-ohmic devices and capacitors [patent_app_type] => utility [patent_app_number] => 16/721006 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5356 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781415 [patent_doc_number] => 20210118494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => STATIC RANDOM-ACCESS MEMORY (SRAM) SYSTEM WITH DELAY TUNING AND CONTROL AND A METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/720888 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16707434 [patent_doc_number] => 10957376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Refresh testing circuit and method [patent_app_type] => utility [patent_app_number] => 16/719930 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3205 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16609059 [patent_doc_number] => 10910072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Accurate self-calibrated negative to positive voltage conversion circuit and method [patent_app_type] => utility [patent_app_number] => 16/717168 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16097855 [patent_doc_number] => 20200202914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SPIN ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/716024 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17062940 [patent_doc_number] => 11107549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => At-risk memory location identification and management [patent_app_type] => utility [patent_app_number] => 16/715468 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 12961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16773762 [patent_doc_number] => 10984881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Memory sub-system self-testing operations [patent_app_type] => utility [patent_app_number] => 16/713108 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10375 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713108 [rel_patent_id] =>[rel_patent_doc_number] =>)