Search

Hyun D Park

Examiner (ID: 15529, Phone: (571)270-7922 , Office: P/2865 )

Most Active Art Unit
2865
Art Unit(s)
2865, 2857, 2863
Total Applications
604
Issued Applications
207
Pending Applications
78
Abandoned Applications
318

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16119203 [patent_doc_number] => 20200211624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => INTEGRATED CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 16/713336 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713336 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713336
Integrated circuit and memory Dec 12, 2019 Issued
Array ( [id] => 17955194 [patent_doc_number] => 11481299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Transmission of data for a machine learning operation using different microbumps [patent_app_type] => utility [patent_app_number] => 16/703142 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703142
Transmission of data for a machine learning operation using different microbumps Dec 3, 2019 Issued
Array ( [id] => 17309977 [patent_doc_number] => 11211101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Differential amplifier schemes for sensing memory cells [patent_app_type] => utility [patent_app_number] => 16/702422 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 31615 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702422
Differential amplifier schemes for sensing memory cells Dec 2, 2019 Issued
Array ( [id] => 16873275 [patent_doc_number] => 20210166742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => PROCESSING MULTI-CYCLE COMMANDS IN MEMORY DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/700212 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700212
Processing multi-cycle commands in memory devices, and related methods, devices, and systems Dec 1, 2019 Issued
Array ( [id] => 16873279 [patent_doc_number] => 20210166746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/700948 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700948
Write operation techniques for memory systems Dec 1, 2019 Issued
Array ( [id] => 16502290 [patent_doc_number] => 10867684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Driving access lines to target voltage levels [patent_app_type] => utility [patent_app_number] => 16/699882 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 12866 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699882
Driving access lines to target voltage levels Dec 1, 2019 Issued
Array ( [id] => 17318507 [patent_doc_number] => 20210407557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Sensitivity Amplifier, Its Control Method, Memory and Its Read-Write Circuit [patent_app_type] => utility [patent_app_number] => 17/280818 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17280818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/280818
Sensitivity amplifier, its control method, memory and its read-write circuit Nov 26, 2019 Issued
Array ( [id] => 15653775 [patent_doc_number] => 20200089418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => MEMORY HAVING DIFFERENT RELIABILITIES [patent_app_type] => utility [patent_app_number] => 16/690384 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16690384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/690384
MEMORY HAVING DIFFERENT RELIABILITIES Nov 20, 2019 Abandoned
Array ( [id] => 16818416 [patent_doc_number] => 11003240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Systems and methods for frequency mode detection and implementation [patent_app_type] => utility [patent_app_number] => 16/684183 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5000 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684183
Systems and methods for frequency mode detection and implementation Nov 13, 2019 Issued
Array ( [id] => 16819672 [patent_doc_number] => 11004509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-11 [patent_title] => Circuit structure and memory circuit with resistive memory elements, and related methods [patent_app_type] => utility [patent_app_number] => 16/677790 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5215 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677790
Circuit structure and memory circuit with resistive memory elements, and related methods Nov 7, 2019 Issued
Array ( [id] => 16865626 [patent_doc_number] => 11024377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Nonvolatile memory apparatus for performing a read operation and a method of operating the same [patent_app_type] => utility [patent_app_number] => 16/677146 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6521 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677146
Nonvolatile memory apparatus for performing a read operation and a method of operating the same Nov 6, 2019 Issued
Array ( [id] => 17032578 [patent_doc_number] => 11094395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Retention voltage management for a volatile memory [patent_app_type] => utility [patent_app_number] => 16/677470 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677470
Retention voltage management for a volatile memory Nov 6, 2019 Issued
Array ( [id] => 16653154 [patent_doc_number] => 10930345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Voltage profile for reduction of read disturb in memory cells [patent_app_type] => utility [patent_app_number] => 16/660590 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4697 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660590
Voltage profile for reduction of read disturb in memory cells Oct 21, 2019 Issued
Array ( [id] => 15503693 [patent_doc_number] => 20200052035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => THREE DIMENSIONAL MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 16/656824 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656824
Three dimensional memory arrays Oct 17, 2019 Issued
Array ( [id] => 15502831 [patent_doc_number] => 20200051604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => APPARATUS AND METHOD OF CLOCK SHAPING FOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/655034 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655034 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655034
APPARATUS AND METHOD OF CLOCK SHAPING FOR MEMORY Oct 15, 2019 Abandoned
Array ( [id] => 16536272 [patent_doc_number] => 10878885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Apparatuses and methods for in-memory operations [patent_app_type] => utility [patent_app_number] => 16/600043 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 30296 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16600043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/600043
Apparatuses and methods for in-memory operations Oct 10, 2019 Issued
Array ( [id] => 15464097 [patent_doc_number] => 20200044873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => SRAM-BASED AUTHENTICATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/594745 [patent_app_country] => US [patent_app_date] => 2019-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/594745
SRAM-based authentication circuit Oct 6, 2019 Issued
Array ( [id] => 15369273 [patent_doc_number] => 20200020401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/580099 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580099 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/580099
Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices Sep 23, 2019 Issued
Array ( [id] => 16609046 [patent_doc_number] => 10910059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Nonvolatile semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/564582 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564582 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564582
Nonvolatile semiconductor memory device Sep 8, 2019 Issued
Array ( [id] => 15938599 [patent_doc_number] => 20200160933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => NON-VOLATILE MEMORY AND TESTING METHOD WITH YIELD IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 16/564010 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564010
NON-VOLATILE MEMORY AND TESTING METHOD WITH YIELD IMPROVEMENT Sep 8, 2019 Abandoned
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