Search

Hyun D Park

Examiner (ID: 15529, Phone: (571)270-7922 , Office: P/2865 )

Most Active Art Unit
2865
Art Unit(s)
2865, 2857, 2863
Total Applications
604
Issued Applications
207
Pending Applications
78
Abandoned Applications
318

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13216315 [patent_doc_number] => 10122538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Antifuse physically unclonable function unit and associated control method [patent_app_type] => utility [patent_app_number] => 15/726470 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5756 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726470 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726470
Antifuse physically unclonable function unit and associated control method Oct 5, 2017 Issued
Array ( [id] => 14163539 [patent_doc_number] => 20190108872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT [patent_app_type] => utility [patent_app_number] => 15/727448 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727448
Area efficient write data path circuit for SRAM yield enhancement Oct 5, 2017 Issued
Array ( [id] => 14332599 [patent_doc_number] => 10297323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Reducing disturbs with delayed ramp up of dummy word line after pre-charge during programming [patent_app_type] => utility [patent_app_number] => 15/726686 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 18022 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726686 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726686
Reducing disturbs with delayed ramp up of dummy word line after pre-charge during programming Oct 5, 2017 Issued
Array ( [id] => 13666655 [patent_doc_number] => 10163500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Sense matching for hard and soft memory reads [patent_app_type] => utility [patent_app_number] => 15/721774 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8604 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721774
Sense matching for hard and soft memory reads Sep 29, 2017 Issued
Array ( [id] => 16692287 [patent_doc_number] => 20210074766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => THREE TERMINAL SELECTORS FOR MEMORY APPLICATIONS AND THEIR METHODS OF FABRICATION [patent_app_type] => utility [patent_app_number] => 16/642865 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16642865 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/642865
Three terminal selectors for memory applications and their methods of fabrication Sep 29, 2017 Issued
Array ( [id] => 16308466 [patent_doc_number] => 10777271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Method and apparatus for adjusting demarcation voltages based on cycle count metrics [patent_app_type] => utility [patent_app_number] => 15/721438 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13655 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721438 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721438
Method and apparatus for adjusting demarcation voltages based on cycle count metrics Sep 28, 2017 Issued
Array ( [id] => 14555255 [patent_doc_number] => 10346088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND [patent_app_type] => utility [patent_app_number] => 15/721674 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 16896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721674 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721674
Method and apparatus for per-deck erase verify and dynamic inhibit in 3d NAND Sep 28, 2017 Issued
Array ( [id] => 14107265 [patent_doc_number] => 20190095308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRAINING PROCESS [patent_app_type] => utility [patent_app_number] => 15/716460 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716460
REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRAINING PROCESS Sep 25, 2017 Abandoned
Array ( [id] => 14078845 [patent_doc_number] => 20190088310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS EMPLOYING CURRENT MIRROR-GATED READ PORTS FOR REDUCED POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 15/711110 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711110 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/711110
Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption Sep 20, 2017 Issued
Array ( [id] => 15170193 [patent_doc_number] => 10490602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Three dimensional memory arrays [patent_app_type] => utility [patent_app_number] => 15/710972 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 9665 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15710972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/710972
Three dimensional memory arrays Sep 20, 2017 Issued
Array ( [id] => 17032550 [patent_doc_number] => 11094367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Semiconductor device with sub-amplifier [patent_app_type] => utility [patent_app_number] => 16/645640 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6912 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16645640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/645640
Semiconductor device with sub-amplifier Sep 10, 2017 Issued
Array ( [id] => 13664493 [patent_doc_number] => 10162406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Systems and methods for frequency mode detection and implementation [patent_app_type] => utility [patent_app_number] => 15/692852 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692852 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692852
Systems and methods for frequency mode detection and implementation Aug 30, 2017 Issued
Array ( [id] => 13819063 [patent_doc_number] => 10186304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Memory device and a clock distribution method thereof [patent_app_type] => utility [patent_app_number] => 15/692132 [patent_app_country] => US [patent_app_date] => 2017-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15692132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/692132
Memory device and a clock distribution method thereof Aug 30, 2017 Issued
Array ( [id] => 12095321 [patent_doc_number] => 20170352414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'PHASE CHANGE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/686308 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4890 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686308
Phase change memory device Aug 24, 2017 Issued
Array ( [id] => 13243097 [patent_doc_number] => 10134758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Memory devices and systems having reduced bit line to drain select gate shorting and associated methods [patent_app_type] => utility [patent_app_number] => 15/683672 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683672
Memory devices and systems having reduced bit line to drain select gate shorting and associated methods Aug 21, 2017 Issued
Array ( [id] => 15547155 [patent_doc_number] => 10573367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Setting of reference voltage for data sensing in ferroelectric memories [patent_app_type] => utility [patent_app_number] => 15/678357 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678357 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678357
Setting of reference voltage for data sensing in ferroelectric memories Aug 15, 2017 Issued
Array ( [id] => 12207401 [patent_doc_number] => 20180052626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'Memory Having Different Reliabilities' [patent_app_type] => utility [patent_app_number] => 15/670436 [patent_app_country] => US [patent_app_date] => 2017-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14341 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15670436 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/670436
Memory having different reliabilities Aug 6, 2017 Issued
Array ( [id] => 13740161 [patent_doc_number] => 20180374550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => READ LEVEL TRACKING AND OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 15/665200 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665200 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665200
Read level tracking and optimization Jul 30, 2017 Issued
Array ( [id] => 12649782 [patent_doc_number] => 20180108425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => ONE-TIME PROGRAMMABLE (OTP) MEMORY DEVICE FOR READING MULTIPLE FUSE BITS [patent_app_type] => utility [patent_app_number] => 15/657494 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657494 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/657494
One-time programmable (OTP) memory device for reading multiple fuse bits Jul 23, 2017 Issued
Array ( [id] => 12595101 [patent_doc_number] => 20180090197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/656876 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656876 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/656876
SEMICONDUCTOR DEVICE Jul 20, 2017 Abandoned
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