Search

Hyun D Park

Examiner (ID: 15529, Phone: (571)270-7922 , Office: P/2865 )

Most Active Art Unit
2865
Art Unit(s)
2865, 2857, 2863
Total Applications
604
Issued Applications
207
Pending Applications
78
Abandoned Applications
318

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14124967 [patent_doc_number] => 10249346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Power supply and power supplying method thereof for data programming operation [patent_app_type] => utility [patent_app_number] => 15/649632 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2611 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649632
Power supply and power supplying method thereof for data programming operation Jul 12, 2017 Issued
Array ( [id] => 13832167 [patent_doc_number] => 20190019568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => FUSE-BLOWING SYSTEM AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/647788 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15647788 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/647788
FUSE-BLOWING SYSTEM AND METHOD FOR OPERATING THE SAME Jul 11, 2017 Abandoned
Array ( [id] => 17862634 [patent_doc_number] => 11443795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => SRAM with address dependent power usage [patent_app_type] => utility [patent_app_number] => 15/648298 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4375 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648298 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/648298
SRAM with address dependent power usage Jul 11, 2017 Issued
Array ( [id] => 13042831 [patent_doc_number] => 10043555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Methods and devices for reading data from non-volatile memory cells [patent_app_type] => utility [patent_app_number] => 15/647166 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15647166 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/647166
Methods and devices for reading data from non-volatile memory cells Jul 10, 2017 Issued
Array ( [id] => 12775678 [patent_doc_number] => 20180150394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => MULTI-MODE CACHE INVALIDATION [patent_app_type] => utility [patent_app_number] => 15/647202 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15647202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/647202
Multi-mode cache invalidation Jul 10, 2017 Issued
Array ( [id] => 14335231 [patent_doc_number] => 10298649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Guaranteeing stream exclusivity in a multi-tenant environment [patent_app_type] => utility [patent_app_number] => 15/629054 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629054 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/629054
Guaranteeing stream exclusivity in a multi-tenant environment Jun 20, 2017 Issued
Array ( [id] => 11983404 [patent_doc_number] => 20170287558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'MEMRISTOR-BASED PROCESSOR INTEGRATING COMPUTING AND MEMORY AND METHOD FOR USING THE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/629714 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 18493 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629714 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/629714
Memristor-based processor integrating computing and memory and method for using the processor Jun 20, 2017 Issued
Array ( [id] => 12614703 [patent_doc_number] => 20180096731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/627562 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627562 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627562
Semiconductor device and operating method thereof Jun 19, 2017 Issued
Array ( [id] => 15488003 [patent_doc_number] => 10559356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Memory circuit having concurrent writes and method therefor [patent_app_type] => utility [patent_app_number] => 15/622738 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15622738 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/622738
Memory circuit having concurrent writes and method therefor Jun 13, 2017 Issued
Array ( [id] => 13098617 [patent_doc_number] => 10068651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Channel pre-charge to suppress disturb of select gate transistors during erase in memory [patent_app_type] => utility [patent_app_number] => 15/621215 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 49 [patent_no_of_words] => 17197 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15621215 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/621215
Channel pre-charge to suppress disturb of select gate transistors during erase in memory Jun 12, 2017 Issued
Array ( [id] => 13111557 [patent_doc_number] => 10074436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-11 [patent_title] => Memory device and data reading method thereof [patent_app_type] => utility [patent_app_number] => 15/620835 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4033 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620835
Memory device and data reading method thereof Jun 12, 2017 Issued
Array ( [id] => 13708751 [patent_doc_number] => 20170365330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/620406 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620406
Semiconductor device Jun 11, 2017 Issued
Array ( [id] => 12848395 [patent_doc_number] => 20180174638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/620678 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620678 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620678
Semiconductor devices Jun 11, 2017 Issued
Array ( [id] => 13613063 [patent_doc_number] => 20180358081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => PUMP SYSTEM OF A DRAM AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/620249 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/620249
Pump system of a DRAM and method for operating the same Jun 11, 2017 Issued
Array ( [id] => 12432918 [patent_doc_number] => 09977487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Dynamic non-volatile memory operation scheduling for controlling power consumption of solid-state drives [patent_app_type] => utility [patent_app_number] => 15/615910 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8916 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615910
Dynamic non-volatile memory operation scheduling for controlling power consumption of solid-state drives Jun 6, 2017 Issued
Array ( [id] => 17047788 [patent_doc_number] => 11100978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Memory unit [patent_app_type] => utility [patent_app_number] => 16/305596 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7993 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16305596 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/305596
Memory unit Jun 1, 2017 Issued
Array ( [id] => 15060991 [patent_doc_number] => 10460807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices [patent_app_type] => utility [patent_app_number] => 15/612294 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7267 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 505 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15612294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/612294
Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices Jun 1, 2017 Issued
Array ( [id] => 13145459 [patent_doc_number] => 10090067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-02 [patent_title] => Data storage device with rewritable in-place memory [patent_app_type] => utility [patent_app_number] => 15/608100 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 6605 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/608100
Data storage device with rewritable in-place memory May 29, 2017 Issued
Array ( [id] => 15388383 [patent_doc_number] => 10535386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Level shifter with bypass [patent_app_type] => utility [patent_app_number] => 15/603252 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3950 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603252 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603252
Level shifter with bypass May 22, 2017 Issued
Array ( [id] => 13042883 [patent_doc_number] => 10043581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Memory circuit capable of implementing calculation operations [patent_app_type] => utility [patent_app_number] => 15/603284 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11794 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603284
Memory circuit capable of implementing calculation operations May 22, 2017 Issued
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